Re: The 2011 release compilation
The error says: fatal error: zlib.h: No such file or directory, zlib is not properly installed, try to install zlib1g and zlib1g-dev on your host.
View Articlevery high precision ADC for whetston bridge
Hi,I want to read voltage of whetstone bridge by using ADC+internal PGA like AD7730but my problem is our strain gauge sensitivity is 100uV/V and strain gauge's supportable excitation voltage is...
View ArticleRe: About ADV7182_RSD.pdf
Dear Dave-san,Thank you very much !!Best regards,Takehiro Yabune
View ArticleRe: Self Latching Comparator
Hi Anna, Thanks for the response. I've attached an updated schematic incorporating your comments. In the schematic, the reset lines from the FPGA are normally tri-stated allowing the voltage output...
View ArticleRe: ADV7623 SPI default mode
We would like to know more detail on the sequence of PWRDNB,SPI and other pins after power-on.Is there any section and timing diagram we should refer to?My understanding is next SPI cycle where ADV7623...
View ArticleRe: AD9106 evaluation board USB driver problem
Hi, I moved this question to the High-Speed DAC community.Someone here should be able to assist you. Best Regards,Sitti
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Re: Questions about SPORTs Interrupt Configuration and Processing by C, and...
Hi Harshit, Thank you very much for your advice to my code using SPORT DMA. It works and I got the real time ADC sample. But I found another issue about the sampling. Thought I set the DMA for reading...
View ArticleRe: BF548 DMA SPORT RX behavior
Hi Sachin, Can the HW engineer also indicate which value of resistor may be better than 33 ohm ?? Just an indication. In all cases , I found a walk around and that is asserting the CS...
View ArticleADV7623 Audio output from SPDIF input
Hello,We are testing Audio performance by using the evaluation board but we got no audio output.Please advise how to fix it.The connection between devices is as follow;1) DisplayLink DL-3500 is...
View ArticleA couple of questions for external device values of AD8334
Dear Sir/Madam, I have a couple of questions for you. As for your external devices AD8334 datahseet 84.5ohm on Fig-85 page-32 ,and 187ohm, 374ohm on Fig-86 page-32,how can I calculate and bring these...
View ArticleRe: CAN sniffer trouble with icoupler ezlINX
when sent message from ezLINX to CAN analyzer: "7F:0D0A20203A202077", the ezLINX poped out an error mesage: "The CAN ID number 1 is invalid" Does anybody know how to set the message ID range? why...
View ArticleRe: Dynamic Range of AD8367
Hi Joel, I have designed the board based on evaluation board and testing it. So the signal level is given is based on my custom board.Both VGAs are working independently but i am facing problem when...
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Re: AD9747 + interposer trouble
Thanks for the response Larry. I'm afraid I have only just come back to this project, hence the delay. TP16: 1.20 VJP16: 3.6 V 10.42 MHz square wave (this seems low?! 250MHz / 24)J5, J8 I see nothing...
View ArticleRe: ADE7880 - Energy measurement
Hi hmani but.. CPF is a signed twos complement register.. In my measure: CPF= 80CB = -32565 dec Power factor = -32565 * 2^-15 = -0.994 ( datasheet pag 56)Power factor is -0.994... it isn't?I don't...
View ArticleRe: Mysterious behavior (ADF4350)
Hi rbrennanI changed the setting of register to the recommended settings you have mentioned But the problem still appeared. I will write down the setting I've used, because the value of the register...
View ArticleSeparated power supplies - ADF4351 as an example
Hi, I had this question about integrated circuits that have multiple power supply pins: the ADF4351 for example, has the SDVDD, AVDD, DVDD, VP, VVCO and VVCO2 pins listed on the datasheet. To minimize...
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Re: ADV212 output abnormal,SCOM[0:3] changes dynamically,dreq0 asserts seems...
Dave，thank you.recently i have checked my readout module, i found some mistakes,and corrected them, i can get some different data now ,it seems like the 202 header and SOC are contained ,but...
View ArticleAD9910 Multi-chip Synchronization
Hi, We have a design using a 1GHz common clock to drive multiple AD9910s’ REF_CLK. The same 1GHz clock also goes to a clock divider chip (TI’s LMK04033) to generate phase aligned 250MHz, 125MHz and...
View ArticleQuestion: Resources used by Sigma divide-by block
(Using Sigma 3.8) I have a design that uses six divide-by blocks, all in near-identical applications. When I check the resources used in the Output window, I see that three of them have twice the...
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Re: Question: Resources used by Sigma divide-by block
Hello Jim, And, "Old age wants to find out", so I tried to duplicate your result in a project with six divides as shown below. Here I got the same 53 instructions for all of them: I'm...
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