Hi rbrennan
I changed the setting of register to the recommended settings you have mentioned
But the problem still appeared.
I will write down the setting I've used, because the value of the register can not
Describe the setting very clearly:
(Note: these setting used for the output frequency we state in the previous discussion)
This setting is for integer mode and the same for the fractional mode with the needed settings:
R0: INT = 1001 | Frac = 0 | address = 0
R1: MOD = 2 (modified) | Phase = 1 (modified) | Address = 1
R2: Counter reset disable | charge pump three state disabled |
Power down disabled | positive phase detector | LDP = 10ns |
LDF_INT (integer mode)| Charge current setting 5mA | Double buffer enabled|
Reference divider disabled | reference double disabled| muxout digital lock detect
Reserved | address = 2.
R3: clock divider = 0 | clock divider off | cycle slip reduction disabled
Address = 3.
R4: output power +5dB| RF output enabled | Aux output power +5dB|
Aux RF output disabled | Aux output select fundamental | mute till lock disabled|
vco DC power on | band select clock divider = 20 | RF divider select DBB 4 |
Fedd back select divided mode | address = 4.
R5: lock detect pin is digital lock detect | address 5.
When i send these information i have lock and both led I am using in the design are on.