Hi Sachin,
Can the HW engineer also indicate which value of resistor may be better than 33 ohm ?? Just an indication.
In all cases , I found a walk around and that is asserting the CS just after starting the clock. This together with lowering the SCLK frequency a little bit , these two things solved the problem. So I am not enabling the CS and SCLK timers at the same time anymore.
The issue has to do with the ADC and not the processor. In my next revision I will avoid sharing pins , because I believe that this increase the load capacitance that can introduce delays. Just by using a probe that has a also a load capacitance influences the system.
Regards,
rschoop