Hi Harshit,
Thank you very much for your advice to my code using SPORT DMA. It works and I got the real time ADC sample.
But I found another issue about the sampling. Thought I set the DMA for reading five ADC values continuously, it read five of every six.
Followed diagram show the timing of the ADC sampling.
In the diagram, the blue trace is DAC output; purple trace is ADC FS (the Low FS for ADC transmitting serially to SPORT1); the yellow trace is the Flag0 of the DSP for clearing the Counter that controls the MUX; and the green trace is the clear of the counter from hardware circuit or Flag0. I also add number for the ADC FS in the diagram.
In the ISR of my code, I use Flag0 to clear the hard counter (just for working reliably, though there is hardware clear pulse) first, and then send the selected ADC to DAC and then re-configure the DMA and restart the SPCTL1.
In the digarm, the counter is clocked by the fall edge of the ADC-FS, You can see the the DMA Interrupt starts at the half of the sixth ADC-FS, and the counter is cleared by the first thing of the IRS, but the hardware Clear is generated at the beginning the fifth of ADC transmitting. I don't know why the DMA interrupt happened at the half of the sixth ADC transmitting (it should have happened soon after the fifth ADC transmission is done.) that makes the sampling miss every sixth ADCs.
I am not sure if the SPCTL1 configuration in my code makes the missing. In fact, I can't say I understand the bits of LAFS,LFS, and FSR very well. Would you please check my configuration to the SPORT1 Control Register or other place to see what make the sampling data lost? And if there is method to avoid the sampling data missing?
Attached is my new code (that just a little bit changing form my last one.)
Many thanks again,
Ning