Hi Anna,
Thanks for the response. I've attached an updated schematic incorporating your comments. In the schematic, the reset lines from the FPGA are normally tri-stated allowing the voltage output from Q/~Q to be transmitted to ~LE/LE. Initially Trigger is less than Trigger_Ref, so Q is low and LE is high (since Q is connected to ~LE and ~Q is connect to LE). When Trigger goes above the reference, Q goes high and LE goes low, latching the output. To clear the output, the FPGA brings ~LE low and LE high through a resistor divider network. Assuming that Trigger is now less than the reference, Q returns low and the FPGA tri-states the reset lines again.
As far as I can tell, this should work correctly except for one possible problem. After the reset when Q returns low but while the FPGA reset lines are still being held high/low, the resistor divider network means that LE/~LE will end up outside the range specified in the datasheet. LE will be approx. 2.8V and ~LE ~1V, for a difference of 1.8V for 1 FPGA clock cycle (~20ns).
So here are my new questions: 1) Does my schematic seem to make sense? and 2) are the transient voltages on the LE pins tolerable? They are still within the Absolute Maximum Ratings but I'd like to make sure.
Thanks for your feedback,
-Schuyler