We would like to know more detail on the sequence of PWRDNB,SPI and other pins after power-on.
Is there any section and timing diagram we should refer to?
My understanding is next SPI cycle where ADV7623 should be slave will start after PWRDNB was disabled.
Is that right?
If there was not any document that describes the sequence please describe it as follow for exsample:
1) Power on.
2) SPI gets into master mode and loads EEPROM data if PWRDNR was low.
3) After EEPROM data load was finished and PWRDNB was disabled, SPI gets into slave mode.
Please distinguish things which is done automatically and ones which require manual operation or user programming.