Re: FMCOMMS1: Clock Genarator adjustments...
Hey Rejeesh... Thanks for your reply... I am sure about 30MHz comes from FPGA and your drivers... I use no-OS.Please have a look on AD-FMCOMMS1-EBZ Functional Overview [Analog Devices Wiki] diagram...
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ad9361_ML605 reference design problem
Hi,I download ad9361_ML605 reference design project from this link,http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/baremetal#downloadsBut i get some errors when i open the...
View ArticleRe: Required Vivado, HDL and FPGA/Linux driver versions for FMCOMMS2/3 with...
I've referred to adi_update_tools.sh and adi_update_boot.sh. You can find more information about these scripts here. Istvan
View ArticleRe: ADV7611 EDID configuration
Hi, I think I solved the problem with the attached configuration. I'd appreciate your review of this file. Thanks,Amir
View ArticleADuCM360 ADC input voltage range by reference
HI, ADuCM360 can select internal reference (1.2V) or external reference (~AVDD).When I select internal reference, ADC input voltage ranges are ±VREF@G=1, ±500mV@G=2, ±250mV@G=4, ...and external...
View ArticleRe: AD9826 strange waveform
The source impedance seems too high to drive the AD9826 switched-capacitor input, and the clamp circuit may not work properly because of its fairly low resistance. Can you try adding a buffer between...
View ArticleRe: AD9364 manually initiated calibrations don't converge (quadrature, cp)
After some trial and error today,the TX Quadrature calibration converges when I set the bandwidth to 10Mhz and force theRx NCO Frequency=Tx NCO Frequency=0.If the bandwidth is set to 1MHz, under the...
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Re: AD9826 strange waveform
Not without redesigning the board. And just where in the data sheet is this info on maximum source impedance? Would a smaller capacitor help?
View ArticleRe: I need positive and negative dc-dc converter
Manu, you could use a SEPIC-CUK topology with the ADP1614 as described in this app note.An Improved Topology for Creating Split Rails from a Single Input VoltageGenerating +/-22V and followed by LDOs...
View ArticleADAU1701 Leaky Mute.
Hello, I wish to use a GPIO controlled mute switch and have used the 'single slew ext volume' block to do so. This sort of works but allows a distorted (attenuated but audible) signal through when...
View ArticleIntermittent Noise using AD9914
I am using the AD9914 eval board in Direct Mode. We have been experience intermittent noise on the output. That is, over a range of output frequencies, we find normal operation (noise floor >40 dB...
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Re: ADF 4036-8 Eval board
The VCO on the ADF4360-8 is actually made up of 8 sub-bands. When VTUNE hits its upper limit, the VCO output switches to the next higher sub-band to achieve the higher frequencies. See the VCO section...
View ArticleRe: Does the AD9625-2.0EBZ work with the Xilinx evaluation board VC707?
Hi Chris-Unfortunately, the AD-FMCADC2-EBZ FMC is the intended evaluation card to interface with a Xilinx development kit.The AD9625-2.0EBZ and AD9625-2.5EBZ have not been tested with VC707.Thanks,Ian...
View ArticleAD9277 AAF question
Hi there, I'm using the AD9277 in an ultrasound application and am wondering about the AAF limitation. It looks like the AD9277 has a 387 kHz lower frequency limit (page 32 of the datasheet here -...
View ArticleRe: boundary box test pattern can't be complete display
Hello, I've asked the expert on this part to come and comment. Dave
View ArticleRe: ADV7181C manual input muxing
Hi Takam, Please refer to the ADV7181C_Configuring_the_ADV7181C_for_RGB_with_external_CSync.pdf document inthe support files (https://ez.analog.com/docs/DOC-1621). Using the configuration described in...
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Re: ADV7611 XGA DVI support
Hi Rajaram, You still haven't answered if the components are sequential or parallel. I believe it'll work in either case for your format, but doubt anyone has ever tried XGA @30hz with the bus...
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Re: ADF4351 settling time calculation using teh EVAL baords
There are two parts to the ADF4351 frequency locking. The first part is the VCO calibration process - this takes 20 µs and set the output frequency within 45 MHz of the desired output. Then, the normal...
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Re: ADF4351 settling time calculation using teh EVAL baords
Before trying the suggestion above, set R3, DB23 (Band Select Clock Mode) to 1 (High). This may be enough if it is currently set to 0.
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