There are two parts to the ADF4351 frequency locking. The first part is the VCO calibration process - this takes 20 µs and set the output frequency within 45 MHz of the desired output. Then, the normal PLL settling takes place. This time varies depending on your loop filter bandwidth (LBW). The default evaluation board LBW is 40 kHz. This produces the following settling time (around 90 µs total):
If you increase the LBW, the normal PLL settling time will reduce. To increase the LBW, you need to change the loop filter components - ADIsimPLL will tell you what values to use. However, you can tweak the LBW by changing the charge pump current setting in Register 2. Increasing the charge pump current will reduce the settling time. On your evaluation board, try setting the charge pump current to 5.0 mA and repeat your lock time measurement. If it still isn't fast enough, you will need to change the filter components. I will show you how.
On your lock time measurement:
- Trigger on LE instead of CLK if possible. You may be losing a few microseconds between CLK and LE. If that's not possible, try viewing the CLK and LE on an oscilloscope and note how much time you're losing between CLK and LE.
- You can also toggle the LDP control in Register 2. This tweaks the timing requirements for Lock Detect to assert.
Take a look at this cheat sheet on the ADF4351, especially the Band Select and Settling Time and Charge Pump Current sections: https://ez.analog.com/message/156447