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Re: ADV7619 HDMI Compliance Jitter Test 8-7 Fails
Re-testing at the lab we find that although the recommended changes have cleared the failures at 222.75MHz and removed the loss of PLL lock condition in some cases at 27MHz, we still have significant...
View ArticleData peculiarities with ADuCM350EKSP
In developing a medical application, I have investigated the use of the ADuCM350EKSP for monitoring respiration. The configuration of the software and data obtained are shown in the attachment. The...
View ArticleADE7880, Problem on handling ZXVA, ZXVB, and ZXVC interrupt
Hello, On ADE7880, ZXVA, ZXVB, and ZXVC are on IRQ1 line. The MCU I used is PIC32. The ADE7880's IRQ1 line is connected to external interrupt pin on PIC32, which is edge triggered, I set it to trigger...
View ArticleADL5391- down-converting mixer
Hi, I would like to use the ADL5391 as a down converting mixer. On the x input I have my measured signal which should be down converted to a fixed frequency (e.g. 10 kHz). This is a symmetrical AC...
View ArticleRe: Noise in PCB
Hi,Thanks for the reply. Yes, I have separated different power signals on different layers of the PCB. I have used planes for different power signals and those planes are spread only on a particular...
View ArticleRe: Migrating from ADAU1701 to ADAU1401
Hi Fernando, It would of course be preferable that an ADI application engineer (or someone who has done the chip swap already) would answer this directly. In the meantime, searching the ADI...
View ArticleRe: AD9901 Phase Detector
Hi,The AD9901 works very well as a stand alone phase detector. It doesn't care a whit about feedback loops. I use it as a phase detector, which drives an ADC.My microcontroller can then do whatever it...
View ArticleIs AD9910 IO_UPDATE line gated by chip select?
Hi,I have a few AD9910s that need to share a common serial port from my MCU. I use chip select to enable serial IO to one device at a time. My question is: Can several AD9910s share a common IO UPDATE...
View ArticleBF609 ethernet DMA Setting by CCES
HIi have questions about ethernet DMA buffer Setting By CCES, i need more DMA buffer to receive multi-connect(24 connects) ethernet packects(4 packets in 30us). because the EMAC Rx buffer only 128...
View ArticleLVDS mode and Half Duplex Mode
We have designed a custom board with a Xilinx Zynq FPGA and AD9361 on it for our wireless application. We have used the Analog Devices FMCOMMS-2 board in combination with the Zed-Board as our reference...
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Re: AD9361 initialization and calibration
It is probably not used by the core, but still being included in the script. Thanks for pointing out, we will clean that up. There is no other branch- this is the only repository and we use the same.
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Re: Noise in PCB
Hi Santosh, To attach your Gerber files, switch to the advanced editor by clicking the link above right:Then click the Attach link at bottom right: Best regards, Bob
View ArticleADV7181D
Hi I have few questions regarding ADV7181D: 1.Does the ADV7181D have the same core as the ADV7181C ? I mean, if the ADV7181C supports a certain input video type and resolution , can I be sure that the...
View ArticleRe: USB-LAN EZ-EXTENDER is not detecting
Dear Colin,Thanks. I tried your suggestion. But still it is not detecting daughter kit. FYI : BF533 EZ-KIT LITE Version Number is 1.6 RegardsJaganathan
View ArticleADV7181D unused digital input pins
Hi Can I leave the VS_IN, HS_IN, FB not connected if I am not using these pins ? ThanksOfir
View ArticleAdvantage of using AD9637 in downgrade mode
Hello, What is the benefit/usage of AD9637 in downgrade mode by setting register values (0x100) in register map? "Resolution/Sample Rate Override (Register 0x100) This register is designed to allow...
View ArticleRe: AD9361 initialization and calibration
Hello, When instantiating the core, can you make sure the following parameters are set to 1: C_CLKS_ASYNC_REQ_SRC = 1;C_CLKS_ASYNC_SRC_DEST = 1;C_CLKS_ASYNC_DEST_REQ = 1; This is the tested...
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Re: Generation of LFM waveform by using POW under RAM modulation mode in AD9910
Hi Kenny G, As you had mentioned in the last reply to set a single FTW before applying the POW updates as per the 2nd term in the phase equation, to do so I used DRG mode to set the 1st...
View ArticleRe: Sweep rate of AD 9956 and AD 9852
Moved this question on the AD9956 and AD9852 to the Direct Digital Synthesis community.
View ArticleRe: LVDS mode and Half Duplex Mode
When D3 of 0x012 is set data ports are configured as unidirectional ports (TDD). With the bit cleared the ports are bidirectional (FDD). Data interface does not change for LVDS mode in FDD vs TDD since...
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