We have designed a custom board with a Xilinx Zynq FPGA and AD9361 on it for our wireless application. We have used the Analog Devices FMCOMMS-2 board in combination with the Zed-Board as our reference design. I have integrated the NO-OS API in the low level SW design and can successfully initialize our board and the AD9361 using our custom SW. I am currently using the AD9361 in FDD mode, LVDS interface and 1T1R mode. I can successfully generate a CW tone with the FPGA and our custom DDS core. The data interface is LVDS and I am using the LVDS timing diagram on page 110 of UG-570 in 1R1T mode to drive the Transmit data interface.
We will want to eventually use this board in a TDD mode application, use pin-mode, and ‘dual synthesizer mode’ disabled to have the best isolation.
If I set the initial parameters frequency_division_duplex_mode_enable= 0 and tdd_use_dual_synth_mode_enable = 0, I can see the driver force Bit-3 of the Parallel-Port-Config-3 register to 1.
Questions:
- 1) When in LVDS mode, and Bit-3 of register 0x12 set, does the data interface change? (UG-671 does not address this).
- 2) If the Data interface does look different with this bit set, can you explain what changes?
- 3) Is it OK to manually clear this bit and run the AD9361 in full duplex mode but with dual-synthesizer mode disabled (while in TDD)?
Thanks.
Allen
