Hi,

It seems that there is indeed some problem with the clock inputs. They are ESD sensitive, so I am assuming something happened to the inputs. Can you measure the clock common mode voltage as close to the pins?

We have a matlab script but i havent tried it with ACE. it has been tested with VisualAnalog which is ACE's predecessor. I will check with our software team and let you know.

Thanks

Umesh

Hello,

I previously used Ad9361 with A10GX and A10SOC, but It failed.

I used branch of hdl_2016_r2 from GitHub - analogdevicesinc/hdl: HDL libraries and projects and tools of  Quartus Prime 16.0 Standard Edition. When I was building the hardward design using the command 'source ./system_project.tcl' on the Quartus Tcl Console, it showed up some error messages listed below

Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_0"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_1"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_2"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_3"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_4"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_5"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_6"
Error (12152): Can't elaborate user hierarchy "system_bd:i_system_bd|axi_ad9361:axi_ad9361|axi_ad9361_lvds_if:i_dev_if|axi_ad9361_alt_lvds_tx:i_tx|altlvds_tx:i_altlvds_tx|axi_ad9361_alt_lvds_tx_lvds_tx:auto_generated"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 44 warnings
Error: Peak virtual memory: 1038 megabytes
Error: Processing ended: Fri Oct 13 11:45:00 2017
Error: Elapsed time: 00:01:01
Error: Total CPU time (on all processors): 00:01:35
Error (293001): Quartus Prime Full Compilation was unsuccessful. 10 errors, 44 warnings

I found some information at Releases · analogdevicesinc/hdl · GitHub about 

'

• The FMCOMMS2 projects on Arria 10 devices is provided as a template ONLY. The project will NOT work on hardware (A10GX or A10SOC) due to Altera's lack of knowledge on their device bank/FMC pin assignments.

'

And I Searched related issues listed below

  Altera SoC support for AD9361,

  Is there a plan to release hdl project supporting Arria10SoC/AD9361?,

  Ad9361 interface to altera,

  AD-FMComms2 HDL support for Altera FPGAs

How can I fix it?

Is there more information or are there materials available which can help me compile the project for FMCOMMS2 + A10GX or FMCOMMS2 + A10SOC ?

Many thanks,

Ethan

Hi,

Only a limited number of the runtime library functions are available to call from within ISRs. Not all C run-time library functions are interrupt-safe (and can therefore be called from an interrupt service routine). For a run-time function to be classified as interrupt-safe:
     • It must not update any global data, such as errno
     • It must not write to (or maintain) any private static data
 
It is recommended that none of the functions defined in the math.h header file, nor the string conversion functions defined in the stdlib.h header file, be called from an ISR as these functions are commonly defined to update the global variable errno. Similarly, the functions defined in the stdio.h header file maintain static tables for currently opened streams and should not be called from an ISR. The memory allocation routines (such as malloc, calloc, realloc, and free), the C++ operators new and delete, and any variants, read and update global tables and are not interrupt-safe; they should not be called from an ISR.
 
The following library functions are not interrupt-safe because they use private static data.
asctime      gmtime      localtime
rand         srand       strtok
 
Please refer the chapter "Calling a Library Function From an ISR" from the below C/C++ Compiler and Library Manual for Blackfin Processors in the below link:
http://www.analog.com/media/en/dsp-documentation/software-manuals/cces-BlackfinCompiler-library-manual.pdf

Regards,

Kader

Hi,

I'm planning to use the ADF5000 prescaler, for frequency conversion of 16GHz to 8GHz, which will be used as LO for down converter.

So, I need the output power variation over the temperature range of -40deg C to +85deg C, for various input power values.

Thx,

measurements on

DVDD1 to GND1, REF1 to GND1,  DVDD2 to GND2, REF2 to GND2:

All points are dead.

I did not yet apply 3.3V on the points you mentioned.

Sir,

I have tried plotting the sine_lut() values which are sent to DAC_DDR_BASEADDR. I treated Q as complex and I as real on matlab.

>> a = complex(i,q)

>> plot(a)

see the result I get. Does this seem Ok to you? shouldn't this be a sine wave?

What's being printed to dmesg when you bind them again?

-Michael

I have returned the board to the vendor.

I'm also interested by controlling VisualAnalog (in addition to ACE)

because I'm working on AD6684 as well.

Thank you

Hi,
Yes it is possible, but we don't support test benches or have documentation on creating one.
If you do want to create a testbench, I recommend you to start start small max one IP/ testbench.
but still you are facing a complex design.
Better understand things from a system level, after that go deeper.
Functional Overview [Analog Devices Wiki] 
AD-FMCOMMS2-EBZ User Guide [Analog Devices Wiki] 
ADI Reference Designs HDL User Guide [Analog Devices Wiki] 
Andrei

Hi Micheal,

i performed dmesg before unbind and again after bind them again. The difference is the following

+cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (9.00.b) at 0x79020000 mapped to 0xe0978000, probed ADC AD9361 as MASTER
+cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (8.00.b) at 0x79024000 mapped to 0xe0976000, probed DDS AD9361
+random: nonblocking pool is initialized

This difference is in the end of the output

-Jan

here is the full output of the dmesg after bind process:

Booting Linux on physical CPU 0x0
Linux version 4.6.0 (root@jan-VirtualBox) (gcc version 5.4.0 (Buildroot 2017.02) ) #2 SMP PREEMPT Mon Oct 9 11:09:45 CEST 2017
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: Xilinx Zynq ZED
bootconsole [earlycon0] enabled
cma: Reserved 128 MiB at 0x16800000
Memory policy: Data cache writealloc
On node 0 totalpages: 131072
free_area_init_node: node 0, pgdat c070b640, node_mem_map dfbb7000
  Normal zone: 1024 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 131072 pages, LIFO batch:31
percpu: Embedded 12 pages/cpu @dfb8e000 s19404 r8192 d21556 u49152
pcpu-alloc: s19404 r8192 d21556 u49152 alloc=12*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 378764K/524288K available (4746K kernel code, 249K rwdata, 1948K rodata, 240K init, 138K bss, 14452K reserved, 131072K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
    lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0691b0c   (6695 kB)
      .init : 0xc0692000 - 0xc06ce000   ( 240 kB)
      .data : 0xc06ce000 - 0xc070c560   ( 250 kB)
       .bss : 0xc070c560 - 0xc072f130   ( 139 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
slcr mapped to e0800000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at e0800100
Zynq clock init
ps_clk frequency not specified, using 33 MHz.
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at e0808000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x82c0 - 0x8318
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xe0880000
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
EDAC MC: Ver: 3.0.0
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 2, 16384 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
Trying to unpack rootfs image as initramfs...
Freeing initrd memory: 2128K (de910000 - deb24000)
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
workingset: timestamp_bits=28 max_order=17 bucket_order=0
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
xilinx-vdma 43000000.axivdma: missing xlnx,flush-fsync property
xilinx-vdma 43000000.axivdma: missing xlnx,addrwidth property
xilinx-vdma 43000000.axivdma: Xilinx AXI VDMA Engine Driver Probed!!
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 143, base_baud = 3125000) is a xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 144, base_baud = 3125000) is a xuartps
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to e081c000
[drm] Initialized drm 1.1.0 20060810
brd: module loaded
loop: module loaded
m25p80 spi32764.0: found s25fl256s1, expected n25q128a11
m25p80 spi32764.0: s25fl256s1 (32768 Kbytes)
8 ofpart partitions found on MTD device spi32764.0
Creating 8 MTD partitions on "spi32764.0":
0x000000000000-0x0000000a0000 : "boot"
0x0000000a0000-0x0000000c0000 : "bootenv"
0x0000000c0000-0x000000500000 : "kernel"
0x000000500000-0x000000550000 : "devicetree_A"
0x000000550000-0x000000ab0000 : "ramdiskimage"
0x000000ab0000-0x000001960000 : "bitstream"
0x000000eb0000-0x000001d80000 : "devicetree_B"
0x000000ed0000-0x000001dc0000 : "devicetree_C"
libphy: XEMACPS mii bus: probed
xemacps e000b000.eth: pdev->id -1, baseaddr 0xe000b000, irq 166
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
e0002000.usb supply vbus not found, using dummy regulator
ULPI transceiver vendor/product ID 0x0451/0x1507
Found TI TUSB1210 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
adv7511: probe of 0-0039 failed with error -5
at24 1-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
hidraw: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
ad9361 spi32766.0: ad9361_probe : enter (ad9361)
mmc0: new high speed SDHC card at address 0007
mmcblk0: mmc0:0007 SD16G 14.5 GiB
 mmcblk0: p1 p2 p3
ad9361 spi32766.0: ad9361_probe : AD936x Rev 2 successfully initialized
spi32765.0 supply vcc not found, using dummy regulator
adf4350 spi32765.0: Probe failed (muxout)
spi32765.1 supply vcc not found, using dummy regulator
adf4350 spi32765.1: Probe failed (muxout)
cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (8.00.b) at 0x79024000 mapped to 0xe087c000, probed DDS AD9361
NET: Registered protocol family 17
Registering SWP/SWPB emulation handler
cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (9.00.b) at 0x79020000 mapped to 0xe0958000, probed ADC AD9361 as MASTER
asoc-simple-card fpga-axi@0:zed_sound: adau-hifi <-> 77600000.axi-i2s mapping ok
adau1761 0-003b: Unable to sync registers 0x4000-0x4000. -5
hctosys: unable to open rtc device (rtc0)
ALSA device list:
  #0: ZED ADAU1761
Freeing unused kernel memory: 240K (c0692000 - c06ce000)
This architecture does not have kernel memory protection.
random: dd urandom read with 69 bits of entropy available
cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (9.00.b) at 0x79020000 mapped to 0xe0978000, probed ADC AD9361 as MASTER
cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (8.00.b) at 0x79024000 mapped to 0xe0976000, probed DDS AD9361
random: nonblocking pool is initialized

Hii,

Thanks for reply. I am using the load cell sensor with sensitivity 2mV/V with excitation voltage of 5 V.

Hi,

What is ADSP-TS201 HRM ?

Hello Rainier,

thank you for your help. We were able to solve the issue. It was a bad frame all along which is why the DAC wasn't showing any response. But now we fixed the problem.

Thanks 

Regards,

Anns

For conductivity measurement we need pure AC excitation. If  we give external pure AC excitation to sensor and  the AD7747  measures impedance  (resistance+capacitance+inductance) using phase locked loop, I can mathematically conclude conductivity.  Refer to CN039 by Analog Devices.

Hi,

Thanks for your answer. It seems that I read the manual too fast and tried to get the refclk to the FPGA by using the J3 connector on the evaluation board, while it should have been the J3 connector on the FPGA board.

Our FPGA board indeed has some SMA connectors available to provide the GT clocks directly.

Kind regards,

Kristof

Does that radio button assign code to the external SDRAM too? Or does it keep that space free unless I assign code there? Does it initialize the external SDRAM differently if I check that button or not?

>> By default the code and data assigned to internal memory unless you assigned it to external SDRAM.

One option to prevent the partitioning of SDRAM into 4 banks in the Linker Description File (LDF) is to do the following:

1)Select "Project" --> "Project Options"

2) In the "Project Options" window, under "External Memory", (which should be present if you chose to create a custom LDF and startup files for your project), select the "None" radio button in the "Partition external memory" box.

3) Rebuild your project.

If you are mapping code and data there, the best approach is to enable "Project Options: Linker: General: Generate symbol map". Build your project and take a look at the <project_name>.map.xml file generated in the output directory in Internet Explorer, and you will see a summary of all the memory sections defined in your LDF, and the used/free space.

If you are placing the heap in SDRAM, the maximum heap size can be the size of the memory block that it is in. That is, if you partition your SDRAM into 4 banks of 4Mbyte (the default is 4 equally-size blocks), the maximum heap size will be 4MByte, as a heap cannot span more than one block. You can set the partition to "Custom" or "None" under Project Options: LDF Settings: External Memory.

Note that no symbols can span multiple sections. So, much like the heap, the maximum size for a global symbol (such as a large global buffer) would be the size of the memory section in which it is being placed.

You can use below option to place the data or code to the external SDRAM.

section("sdram0")
<code to be placed in SDRAM>

 If I have a pointer that is set to point to addr 0x00000004 (so it's not a null pointer), what is the behavior if I don't have SDRAM initialized correctly?

>> When you connect to a target via a JTAG Emulator or Debug Agent, the default behavior is that the Emulator will check a corresponding XML file to see if there is any configuration to be done of the EBIU/External Port/DDR. This feature is enabled/disabled via:

[VisualDSP++] “Settings: Target Options: Use xml reset values”
[CrossCore Embedded Studio] Under the "Custom Board Support" tab within the "Run: Debug Configurations" menu

If you are using Ez-Kit, the VDSP++ tool uses the .xml files for initializing the SDRAM controller before loading the data. By default the .xml file has the value corresponds to the SDRAM on the EZ-KIT Lite board. You may need to change the SDRAM control register values as per your SDRAM to make it work on your custom board. The .xml files for ADSP-BF561 is available on the below path:
C:\Program Files (x86)\Analog Devices\VisualDSP 5.1.2\System\ArchDef\ADSP-BF561-proc.xml

When booting the SDRAM initialization to be done in the Inti file.

 I do not currently have "SDRAM bank 0 in use" checked in the compiler settings. Would this make a difference in how my code accesses data?"

>> I did not understand it well, could you please elaborate what exactly you are trying to ask?

Thanks,
Jithul

Looks like it should be-

We haven't looked at that combination, so don't know.

What is it that you can't find out yourself?

Any MMCX mating connector will work:

Samtec make some. So do Amphenol and Molex. 

Search around those places, and you are likely to find something you need.

That is the only way (SPI)-

The level translator is getting the power?

Did you check all the devices are getting their power?

What hardware is this?

I don't think we have any such thing.