↧
Re: Is the JESD204 core complete?
↧
Re: ADV7180：the video quality has some problem
Hello,
I assume your setup is NTSC camera -> ADV7180 -> FPGA.
Note that the ADV7180 requires a 28.63636 MHz crystal clock with an accuracy of 50ppm.
The line locked clock (LLC) output from the ADV7180 is 27MHz +/- 5%. The LLC varies to compensate for horizontal lines of analog video that are longer/shorter than standard.
The artifacts around the writing in the image above are unfortunately standard for the ADV7180. These are luma/chroma separation artifacts. The ADV7180 is designed to have minimal latency delay so it has a 2D comb luma/chroma separation filter. This unfortunately will result in artifacts.
It is possible to get better performance by using a part that has a 3D comb luma/chroma separation filter such as the ADV7850. This will result in significant latency delay and extra cost.
regards,
Robert Hinchy
Applications Engineer
Analog Devices Inc.
↧
↧
Re: EVAL-AD5372 as standalone DAC
@kausban sorry your Arduino Sketch is buggy :/
First: there are no two sync lines with AD537x. There are groups 0-4 maximum
Did you understand what the X1A (B), C, M registers are?
You load values into these registers X1A (B) = Value for selected A or B registers. M = multiplication and C = channel offset register. These values are calculated and go to the selected X2A or X2B register for a falling edge / LDAC
The respective A or B register is used for fast toggling
as last: "else if (inbyte == '@') ..." and other constructs can be solved better with switch-case
↧
Re: JESD link is not working on DAQ2 and ZCU102 hardware setup
Hi Rejeesh,
Thanks for giving us heads up. we will get the latest dev of today. Again, will let you know what we get.
Cheers,
James
↧
Re: How do I communicate with the AD4350 on the AD9739A-FMC-EBZ?
Hi Rejeesh,
Yes, power looks good on U1(AD3308). Both VCCA(2.5V) and VCCY(3.3V) are good.
I have 2 AD9739A-FMC-EBZ boards and they both behave the same way.
I am going to remove U1 from one of the boards to see if the signals look ok without U1.
Thank you for any help or ideas you can provide!
Kerry
↧
↧
Re: Error occurred while connecting AD9361 to MATLAB
thank you, it helped me.
but now I have another problem. when I run the model, the data is transmitted some time and then Simulink hangs without any error message. I have to close Matlab from task Manager. could you help me?
↧
Re: ADUA1462 Program and Data memory size
Thank you for pointing out these important errors in the documentation. Table 3 is correct. The ADAU1462 has 16 kWords of program memory. Here is the corrected version of Table 58:
This is the corrected version of Figure 89. Note that it is identical to Figure 26:
This is the corrected version of Figure 90. Note that it is identical to Figure 27:
Thank you for this errata report. A revised data sheet will be posted to the web site soon. Please let me know if you have any additional questions.
Ken
↧
Re: ADF4158
You can find more information here...
↧
Re: Can't find IIO devices for KC705 and FMCOMMS3
Here is the output:
↧
↧
Interaction Between two ADF5355 Synthesizers
Hello,
I have been using the ADF5355 Synthesizer IC in a single-channel tuner product for several years, and have had no issues until I designed a two-channel version of the product.
In the two-channel version, there are two identical ADF5355 synthesizers on the same PCB with a mechanical chassis isolating the two sections. The two ADF5355 IC's are on separate regulated power supplies, and share only the SPI interface and the 16 MHz reference source. There is no requirement for a predictable phase relationship between the two channels, although they are typically tuned to different frequencies, but could be tuned to the same frequency.
When tuning to the same frequency, the problem I observe is large spurious sidebands that pop up inside the loop bandwidth and are extremely sensitive to temperature, and proximity of the chassis. The offset frequency of the sidebands is not predicable and shifts dramatically with proximity of the chassis or your hand. The sidebands act like an oscillation caused by some sort of feedback loop or instability. They also can disappear/reappear after repeated tuning commands. Several in-between states can be seen, where the noise just increases without the discreet sidebands popping up. Installing the PCB into the chassis does not eliminate the issue. Removing power from one of the channels eliminates the problem in the remaining channel. It appears that there is some sort of interaction/feedback loop between the two channels.
Here is a list of things I've tried:
1) Added pads at the REF inputs to increase the isolation between chips.
2) Added chokes to the REF inputs.
3) Adjusted the REF input level across the recommended operating range.
I would appreciate any thoughts or suggestions you have.
Best regards,
Chuck Beam
↧
Re: When is the adau1466 avialable?
The ADAU145x and ADAU146x family are very similar. Both have substantially more powerful cores than the ADAU144x family. The '62 and '66 and code pin compatible, drop-in replacements for the ADAU1452. The differences are (a) substantially more memory, (2) the S/PDIF transmitter and receiver now support speeds up to 192 kHz, and (c) bug fixes in the ASRCs. The ADAU1463 and ADAU1467 are in slightly larger packages. They provide much more serial audio I/O flexibility with the addition of eight additional data pins that can be configured as inputs or outputs, more MPx (GPIO) pins, and two additional AUXADC channels.
Ken
↧
Re: Can't find IIO devices for KC705 and FMCOMMS3
Do you have any devices (file descriptors) in /sys/bus/iio/devices/ on the target device? Just run "ls -l /sys/bus/iio/devices/" from the same serial console.
-Travis
↧
Re: ADAU1466 compiler error?
SigmaStudio version 3.15 has been released and includes a fix for this bug. You can download the software here.
Ken
↧
↧
Re: ADRV1CRR-BOB GPIO Usage (I2C, SPI, PWM)
Rejeesh,
So, if I understand correctly, I can attach my I2C sensors to the pins mentioned on that GitHub (AF24 and AF25) and then the devices should work?
How can I locate those pins on the BOB? Is there a diagram somewhere?
Thanks again,
Jacob Hempel
↧
Re: ADRV1CRR-BOB GPIO Usage (I2C, SPI, PWM)
Jacob,
Look at the schematics-
This may not be the latest version- but as a reference, this is what I get if I parse the cadence net list to find the mappings.
U1,AF24,IO_L5P_T0_13,SCL, JX2.17.N9 R58.2.N2 U21.2.SCLA
U1,AF25,IO_L5N_T0_13,SDA, JX2.19.N10 R57.2.N2 U21.3.SDAA
So whatever your carrier is (break out or your own), if the module is SOM2 and you want another i2c device on the system, connect that device to JX2.17/JX2.19 (of course you need to match the voltages).
↧
Re: Can't find IIO devices for KC705 and FMCOMMS3
No, there's nothing on there.
Here's the output from dmesg:
Ramdisk addr 0x00000000,
Compiled-in FDT at 80341c58
Linux version 4.0.0-g1610de3 (jenkins@romlx1) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #57 Wed Apr 20 12:06:23 IST 2016
setup_cpuinfo: initialising
setup_cpuinfo: Using full CPU PVR support
wt_msr_noirq
setup_memory: max_mapnr: 0x30000
setup_memory: min_low_pfn: 0x80000
setup_memory: max_low_pfn: 0xb0000
setup_memory: max_pfn: 0xb0000
Zone ranges:
DMA [mem 0x0000000080000000-0x00000000afffffff]
Normal empty
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000080000000-0x00000000bfffffff]
Initmem setup node 0 [mem 0x0000000080000000-0x00000000bfffffff]
On node 0 totalpages: 196608
free_area_init_node: node 0, pgdat 8042f688, node_mem_map 81000000
DMA zone: 1536 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 196608 pages, LIFO batch:31
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 195072
Kernel command line: console=ttyUL0,115200
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 768052K/786432K available (3335K kernel code, 124K rwdata, 788K rodata, 6211K init, 84K bss, 18380K reserved, 0K cma-reserved)
Kernel virtual memory layout:
* 0xffffe000..0xfffff000 : fixmap
* 0xffffe000..0xffffe000 : early ioremap
* 0xb0000000..0xffffe000 : vmalloc & ioremap
NR_IRQS:128
/amba_pl/interrupt-controller@41200000: num_irq=16, edge=0x412
/amba_pl/timer@41c00000: irq=1
xilinx_timer_set_mode: shutdown
xilinx_timer_set_mode: periodic
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949672950ns
Calibrating delay loop... 49.56 BogoMIPS (lpj=247808)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
devtmpfs: initialized
NET: Registered protocol family 16
Switched to clocksource xilinx_clocksource
xilinx_timer_set_mode: oneshot
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 512 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
XGpio: /amba_pl/gpio@40000000: registered, base is 480
XGpio: /amba_pl/gpio@40000000: dual channel registered, base is 448
Skipping unavailable RESET gpio -2 (reset)
futex hash table entries: 256 (order: -1, 3072 bytes)
jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
40600000.serial: ttyUL0 at MMIO 0x40600000 (irq = 4, base_baud = 0) is a uartlite
console [ttyUL0] enabled
brd: module loaded
Xilinx SystemACE device driver, major=254
xilinx_lcd 40010000.gpio_lcd: Device Tree Probing 'gpio_lcd'
xilinx_lcd 40010000.gpio_lcd: LCD 0x40010000 mapped to 0xb0160000
60000000.flash: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000089 Chip ID 0x008962
NOR chip too large to fit in mapping. Attempting to cope...
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Using buffer write method
Using auto-unlock on power-up/resume
cfi_cmdset_0001: Erase suspend on write enabled
erase region 0: offset=0x0,size=0x20000,blocks=1023
erase region 1: offset=0x7fe0000,size=0x8000,blocks=4
Reducing visibility of 131072KiB chip to 32768KiB
4 ofpart partitions found on MTD device 60000000.flash
Creating 4 MTD partitions on "60000000.flash":
0x000000000000-0x000001380000 : "fpga"
0x000001380000-0x000001400000 : "boot"
0x000001400000-0x000001440000 : "bootenv"
0x000001440000-0x000002000000 : "image"
xilinx_spi 44a70000.axi_quad_spi: at 0x44A70000 mapped to 0xb21a0000, irq=10
libphy: Fixed MDIO Bus: probed
xilinx_emaclite 40e00000.ethernet: Device Tree Probing
libphy: Xilinx Emaclite MDIO: probed
xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:02
xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xB003C000, irq=2
i2c /dev entries driver
i2c i2c-0: Added multiplexed i2c bus 1
at24 2-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
at24 2-0054: 256 byte 24c02 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 2
at24 3-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 3
i2c i2c-0: Added multiplexed i2c bus 4
i2c i2c-0: Added multiplexed i2c bus 5
i2c i2c-0: Added multiplexed i2c bus 6
i2c i2c-0: Added multiplexed i2c bus 7
i2c i2c-0: Added multiplexed i2c bus 8
pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
ad7291: probe of 3-002f failed with error -5
platform 79020000.cf-ad9361-lpc: Driver cf_axi_adc requests probe deferral
ad9361 spi0.0: ad9361_probe : enter
ad9361 spi0.0: ad9361_probe : Unsupported PRODUCT_ID 0xFF
platform 79024000.cf-ad9361-dds-core-lpc: Driver cf_axi_dds requests probe deferral
TCP: cubic registered
NET: Registered protocol family 17
platform 79020000.cf-ad9361-lpc: Driver cf_axi_adc requests probe deferral
platform 79024000.cf-ad9361-dds-core-lpc: Driver cf_axi_dds requests probe deferral
Freeing unused kernel memory: 6208K (80431000 - 80a41000)
xilinx_emaclite 40e00000.ethernet eth0: Link is Down
xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
random: ssh-keygen urandom read with 61 bits of entropy available
random: nonblocking pool is initialized
↧
Re: About AD-FMCDAQ2-EBZ HDL programming
Hi Rejeesh,
I went through the reference design, it is too complicated for my application, I just want to send/collect the data at the JESD204 interface. I am trying to figure out if you send any commands through the SPI interface to initialize or configure the ADC/DAC, but I did not find those codes, maybe I missed something. Are there any configuration codes in the reference design?
Actually I built a very simple module with only a JESD204 core and JESD PHY core, I used the 500MHz reference clock from DAQ2 as the qpllclk of JESD PHY core. During my in-system debug, I did not see any clock signal from qpllclk or the TXOUTCLK port of JESD PHY core. So my question is, does DAQ2 start to provide this 500MHz clock as soon as it is plugged into HPC port and the FPGA is powered on? Or I need to turn on DAQ2 by sending some initialization commands through the SPI interface first?
↧
↧
Re: 1SPS mode of ADT7311
Hi,
That is, in one-shot and 1 SPS modes, we must write to the operation mode bits to reset the /RDY bit, reading from temperature value register in these two modes won't reset /RDY bit, right?
IMHO, the 1 SPS mode work like below:
After configured to 1 SPS mode (write to mode register), the /RDY bit is reset to 1. Then every second, ADT7311 generate a new reading. After reading the temperature, /RDY goes to low. But no need to rewrite to mode register.
But, according to your answer, the working flow should be like below:
- t = 0, set it to 1 SPS mode, /RDY = 1;
- t = 60ms, the new data is ready, then /RDY = 0
- t = 1010ms, read the temperature register, still /RDY = 0
- t = 1205ms, write to mode register to set it to 1 SPS again, then /RDY = 1
- t = 1265ms, the new data is ready, then /RDY = 0
- ......
So, the 1s timer in the ADT7311 always reset after a writing to mode register, Right?
Thanks.
↧
Re: some questions about ADF5901 and ADF4159
Hi,
I have a question to consult obout Tx output power.
What is the function of REFin in ADF5901? The datasheet shows that it relates to VCO frequency calibration, does it relate to Tx outout power? I use ADF4159 and ADF5901 to get 24GHz , in my PCB board, the REFin pin of ADF5901 is suspended and has no input signal, and the Tx1 output power is still only -16dBm. I wonder the Tx output power is decided by the power of REFin pin and my design is wrong? The register1 of ADF5901 is the amplitude calibration reference code, so the power of REFin pin is the reference value for TX output amplitude calibration code?
What is the registers writing order after initialization sequence? Does the recalibration sequence decide the Tx output power?
Thank you very much.
↧
Re: how to adjust output power of the adf5901?
Hi,
I have some questions obout Tx output power.
1. Does the REFin in ADF5901 relate to Tx outout power? I use ADF4159 and ADF5901 to get 24GHz , in my PCB board, the REFin pin of ADF5901 is suspended and has no input signal, and the Tx1 output power is still only -16dBm. I wonder the Tx output power is decided by the power of REFin pin and my design is wrong? The register1 of ADF5901 is the amplitude calibration reference code, so the power of REFin pin is the reference value for TX output amplitude calibration code?
2. What is the registers writing order after initialization sequence to get max output power? Just need write R0 and R1? What is the function of recalibration sequence? Does it decide the Tx output power? I notice that R7 should be 2A20B929 in datasheet, but only set to 2800B929 can the board work, why?
Thank you very much.
↧