Hi Jose,
If you refer to the following figures from the datasheet. ADM1186 ensures that the outputs are always in a known state when Vcc > 1V. For supply voltage(Vcc) from 1V to VUVLO the outputs are driven low to ensure that the regulators are not unexpected enabled.
When Vcc is below 1V the state of the output of ADM1186 is not guaranteed. Please check the specification of the regulators to make sure the minimum voltage before they start to regulate is greater than 1V.
Regards.
Opal
Hi Susan,
There is a video explaining how and why the levels work the way they do here: Video
And there is a short article on the drive capabilities for cables on each side of the ADuM1250 here: Article
If the ADM3260 channel and dc/dc converter orientation is not correct for a certain application, you may need to use an ADuM1250 and ADuM5000.
Regards,
Jason
Thread safety requires a bunch of things, such as locking access to API calls that require exclusive access to devices (like SPI). We're comfortable with all of that, but as mhennerich points out, we need that per-instance handle, or some kind of context. Whenever we pass in a spiSettings_t, or a mykonos_device_t, we can fake that out. For those functions that don't take such an argument, we're stuck.
Simply not supporting multiple AD9371 is not an option.
Config time (via EEPROM) for the ADN4612?
it appears that the ADV7613 reports that sync channel 1 stdi measurement are not valid looking at the dump file you gave
adv7613_dumpreg: dev = 0x44, addr=0xb1, data=0x3f
adv7613_dumpreg: dev = 0x44, addr=0xb2, data=0xff
Can you forward on the EDID file? Thanks.
We are noticing a 5dB degradation in IP3 at temps below -25C. The amplifier is operating at 200MHz with the recommended external components. Thoughts?
When I came to the SDK application, after adding directories, there is an error:
Description Resource Path Location Type
'XPAR_AXI_DAQ2_GT_BASEADDR' undeclared here (not in a function) ad_fmcdaq2_ebz.c /fmcdaq2/src/ad-fmcdaq2-ebz line 74 C/C++ Problem
Hello all,
I am using the AD9680 with the no-OS daq2 software (ZC706). I havent changed anything in the FPGA hardware.
It is my own pcb design. My setup is the following one:
- FADC = 491.52MHz
- SYSREF ADC = 7.68MHz
- M=2
- L=4
- FADC_FMC = 491.52MHz
- SYSREF_ADC_FMC = 7.68MHz
I cannot pass the test of the sync lane (jesd204b_gt_en_sync_sysref(ad9680_gt_link);)
Here are the results:
AD9680 PLL is locked.
AD9680 successfully initialized.
JESD204B successfully initialized.
JESD204B-GT-RX[3]: Invalid status, received(0x0FFFF), expected(0x1FFFF)!
JESD204B-GT-RX[2]: Invalid status, received(0x0FFFF), expected(0x1FFFF)!
JESD204B-GT-RX[1]: Invalid status, received(0x0FFFF), expected(0x1FFFF)!
JESD204B-GT-RX[0]: Invalid status, received(0x0FFFF), expected(0x1FFFF)!
Is my configuration correct regarding the FPGA reference design (hdl_2015_r2)?
Do you have any idea of what I should check? SYSREF delay?
How do you relate the hdl setup to the software setup, frequency setup speaking?
Thank a lot.
Best,
Chris
Hi Vishnu,
Jitter from the clock source certainly is aculprit but may not be the only reason for SNR degradation.
Thanks
Umesh
Hi,
A few things about the waveforms you show on the oscilloscope.
The thing about the status bits is that once they are set, they hold the value until it is cleared by writing a 1 to the respective bit. None of those bits are too helpful for understanding what is going on but it is worth you using the LENERGY bit in STATUS0 to see when the energy registers have been updated with new values.
Regards,
Dlath
The only way you'd be able to address this at all would be to use the clear phase accumulator function on both DDS's at the same time, but this does not address the inherent problem, the devices will always drift if they are clocked by different time domains.
The only way to insure that the two channels do not drift relative to one another is to clock them from a common source.
The AD5390 does not have the DDS engine built into it, so you would need something external. The closest thing we have with DDS built in is the AD9959 (4 channels, they can be updated simultaneously)
Hi Christian,
Awesome - I went ahead and set up a TCB Receive block set for SPORT1B, I'd like your input on if anything else ought to be modified to the file - also in "blockProcess_audio.c", I set up another pointer with the SPORT1B receive blocks, and had the floatData use that pointer instead, filling Rx_L2 and Rx_R2 with data from TCB_RxBlockB_A0 and TCB_RxBlockB_A1.
My concern is whether the pointer in "blockProcess_audio.c" is correct, and if I have the right parameters set up for the second set of TCB blocks within "initSPORT01_TDM_Mode.c". I made sure to attach the two revised files as well. I've been actively researching this, and my background is more focused on Electrical Engineering - thank you for bearing with me, it's been a definite learning process!
Thanks Again,
Jordan
I have a Hittit IC Amp Driver (HMC326M8G) and I'm having a hard time reconciling the date code. The part is marked 3503 and the cert says 1538. Do you have a chart that deciphers date codes? Donna.
Hi,
Yes, you can put the noise reduction capacitor between pin 4 and pin 8, and I would also put a capacitor between pin 4 and pin 6 (the circuit board ground). Be sure to observe the note under Figure 17 regarding the net current through the AD587.
Walt
In terms of output pins such as CF1, CF2, IRQ, ZX_I, ZX and REVP, the mosfet is there in order to drive the LED because the outputs can't directly drive an LED. If they are not being used then you can just leave these pins floating, if its being sent to the MCU then the 10KOhm pull-up is enough.
Thanks for your reply.
If I want to have 16 channel waveform generator, would I then need to use 4 x AD9959 or can I use the AD5390 in conjunction with the AD9959. I actually just want to be able to output sine waves, square waves, triangular waves at frequencies up to 20kHz. Any recommendation?
Thanks!
In a prior topic from about a year ago (AD9779A Timing Optimization), a member of the ADI staff replied that "The AD9779A automatic timing optimization mode does not work. Please do not use it."
Can somebody please provide more detail about this? Does it fundamentally not work for all cases, or is the problem more nuanced? I have this enabled in a prior project and would like to understand the ramification.
Also I cannot find any errata documentation for this part - where would I find a list of part errata such as this?
Thank you.
Dear Steve,
I now have a lot of experience with the AD9578, however I have a programming problem:
The device sometimes fails to lock properly ( unstable frequency a few kHz low) after repeating a programming sequence with the same values. The sequence I use is:
1/- toggle MR bit
2/- program all registers
3/- read and print all registers
The device is now locked and outputting the correct frequency
Now repeat the above sequence with exactly the same register values
The device is now in the unstable lock mode
The read back of the registers gives identical values.
Repeating the sequence always gives an incorrect lock.
This problem occurs both in rational and fractional modes.
After the master reset, should the device be in exactly the same default state?
Note that programming after a power on reset gives a correct lock. Also programming a completely new frequency sometimes resets the stuck mode.
best regards
Cosmo Little