Thanks for the reply.
Out of curiosity, is this information posted anywhere for me to take a look to learn more on how to use the fmcomms sink/source blocks?
-Tellrell
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Re: GNU Radio Issue with FMCOMMS3
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Re: adm1087
No, the capacitor does not discharge after t = 60, it only discharges when ENIN goes high (active low) or Vin drops below 0.6V. In your test when t = ~3 min you're removing Vcc while ENIN is low as a result the capacitor is not getting completely discharged, and you're seeing the variation in time delay next time you're powering up.
As a test, if you drive ENIN high before powering down, the capacitor should be fully discharged and you should see the expected time delay (~60s) next time you're powering up.
Regards,
Opal
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Re: ADPD 105 input configurations
Hi Simon,
I think the problem has to do with the settings in the ADC offset registers 0x18,19,1A,1B for timeslot A and 0x1E,1F,20,21 for timeslot B. The way the part works is that for 0 input current when operating in "normal mode", the ADC output will be at ~midscale +/- some internal offsets. So if the ADC offset registers are set to 0, you should see each of the channels at ~8192 codes per pulse. With a setting of 0x2710 you'll certainly be railing the output of the device at 0 for no input, and even for some amount of signal as you start to flash the LEDs. The way to rectify this is to null the offset at a value that sets the output of the device at ~0 when there is no input to the device. I would follow these steps in order to do this:
1. Set the number of pulses for timeslot A and B to 1. You could do this for a greater number of pulses, but then you would have to just factor out the number of pulses from the measurement so it's easier to just set it to 1 pulse (register 0x31 and 0x36).
2. Turn the LEDs off
3. Make sure the ADC offset registers listed above are set to 0.
4. Make a measurement of the output of each of the channels. This should be ~8192, give or take some amount of codes due to internal offsets.
5. Set the ADC offset registers to some value to null out this offset. For example, if you measure 8043 codes in step 4, then you would set the ADC offset register for that channel to 0x1F6B. Or maybe something a little less than that if you want to be able to measure the noise at 0 input without clipping the output.
Once you've set all the ADC offset registers appropriately you should see the device work as expected. The rest of your register settings looked OK to me at first glance.
Regards,
Kevin
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Re: General DDS Question
So the AD9106 has the option of simultaneously updating all 4 DACs then?
What is the difference between the AD9106 and the AD9959 in terms of performance? Tuning word vs. DAC resolution, what effect does that have?
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Re: General DDS Question
Hi -
The AD9959 had four independent DDS blocks, one for each DAC. The AD9106 has one DDSS shared by all four DACs.
Thanks
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Re: General DDS Question
DAC resolution is primarily responsible for establishing the level of the noise floor. Tuning word sets the step size between adjacent available frequencies.
The AD9959 will not inherentlyoutput a sawtooth waveform; the angle to amplitude algorithm it utilizes restricts the output of its DAC to sine waves. Having said that, it is actually possible to set the AD9959 up to generate a sawtooth using the amplitude sweep function, but that would reduce the resolution down to the width of the Amplitude Scale Factor (10bits).
The AD9959 devices are pretty easy to synchronize, so you can set them up so that any updates to channels occur simultaneously.
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Re: Using HMC247/877 at 3GHz ?
Hi hma,
Good news! For the HMC247 I was able to locate some S-Parameter vs. Vctl data as low as 0.05 GHz.
I've processed the +25C data into a flat file that can be easily imported into Excel or other application capable of reading .txt files.
This data set will show you how much of a 3.0 GHz phase shift can be obtained through variation of the Vctl voltage from 0V through 10V.
Let me know if you need additional help interpreting the data.
Regards,
SMcBride
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Re: adm1087
OK. I understand now.
That makes sense.
Thanks for your help.
Shang
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DSSS - Link computation
Hi,
This query came up while doing the link calculations for the DSSS-OQPSK mode (IEEE 802.15.4-2006). ( hardware: ADF7242).
It says in the data sheet of adf7242 that the receiver sensitivity is -95dBm for the DSSS-OQPSK mode. Should I add the processing gain when computing the final Link margins or is this inclusive of the processing gain (in the SNR itself).
Especially important for me as the RF signal strength at the receiver is expected to go down to -95dBm.
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Re: AD5933 / AD5934 stuck in program-flow, DFT does not complete
Hi Brac,
I have the same issue. how did you solve?
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Generating overtones with fixed phases in SigmaDSP processors
Dear colleagues!
I would like to share my experience in generating overtones of the sine tone (harmonics) with fixed phase relationships in SigmaDSP processors. For example if we need to generate sine tones sin(wt), sin(2wt), sin(3wt),... with the strictly specified phase relationships, it will be not enough to use sine tone generators from the toolbox of SigmaStudio. Even if we will specify the initial phases, these generators will not keep phase relationships intact and their phases will be permanently shifting. Even if we will generate equal tones using two generators with the same initial phases, the shift between their phases will permanently change.
Usually to generate overtones of the fundamental frequency with the fixed phase relationships, engineers use multiplication of sine tones by itself and summing the products with different coefficients. For example, sin(2x)=1-2(sin(x-pi/2))^2, sin(3x)=3sin(x)-4(sin(x))^3. But these techniques are pretty bulky and are not universal. What if we need to generate any arbitrary overtone of sin(x), for example sin(5x) or even sin(1,5x)? It will be hard enough to realize it using restricted resources of SigmaDSP. Moreover the amplitudes and phase relationships of the products are hardly predictable.
But this is not the problem for SigmaDSP to generate any sine tone the same way as it is realized in modern DDS IC's. We need the sawtooth generator, which will serve as the phase accumulator, and the lookup table (LUT) with the sine wave values. When the level of the sawtooth generator is equal to the index of the LUT, the output of the LUT will be equal the value of the element with this index. In this manner we can generate signals with any forms and phases. The number of points of the LUT of sine wave must be odd, and the last point must be equal to the first. The frequency of the sawtooth generator must be equal to the required frequency of the sine tone. In the three LUTs there are three tones sin(x), sin(2x), sin(3x). Their phase relationships are strictly specified in LUT. Because the value of the sawtooth is changed between -1,..,+1 we need to lift it above the zero, so we add 1 Volt DC and multiply it by 0.5. After this manipulation the output of the sawtooth will change between 0,..+1, which is equal to the indexes of the LUT with the fractional input. It is also possible to use LUT with the integer input, in that case we should multiply the sawtooth by half of the LUT's size, in my example it is 96, so the input of the LUT will change between 0,...,+193. But there is an issue, if the frequency of the sawtooth generator is not integer divider of the Fs then the generation of sine tone will not be very smooth, and SFDR of such sine generator will not be very good.
With best regards!
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Re: How to acess to normal mode for my ad9234?
Hi.
The question is:Using the test mode before, do i need to do a soft reset to acess normal mode?
-Yes. For the AD9234, a transition from test modes (Register 0x573 ≠ 0x00) to normal mode (Register 0x573 = 0x00) requiresan SPI soft reset.
Umesh
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How exactly do you program external SPI flash via the JTAG interface with ICE?
Hi there,
I'm currently developing for the BF592 processor and am using the JTAG interface for loading and debugging my application. However, I would like to transition over to a 'boot from SPI flash' mode. This would require me to place a loader file onto my external SPI flash.
My question: what kind of utility tools does CCES offer to program my external flash via the JTAG interface given that I'm using the ICE-1000?
Thanks!
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Re: Noise reduction for negative reference
Dear Walt,
yesterday I put the noise reduction capacitor in my circuit, but the result was more noise than without.
See attached a table of the changes and the results:
In line 1 is the result of my original setup.
Second line shows the improvement with a bgger Capacitor between AD587 Pin4 and ground.
BUT: afterwards I added the noise reduction capacitor, and the noise improved only at Pin 4; at the non inverting input of OP27 and at the output of Op27 the noise deteriorated remarkably.
Do you have an explanation or even a cure?
I would really appreciate your opinion!
Regards,
Guenther
Von: Walt_Kester
Gesendet: Donnerstag, 16. März 2017 19:15
An: Angst Günther
Betreff: Re: - Re: Noise reduction for negative reference
EngineerZone <https://ez.analog.com/?et=watches.email.thread>
Re: Noise reduction for negative reference
reply from Walt_Kester<https://ez.analog.com/people/Walt_Kester?et=watches.email.thread> in Power Management - View the full discussion<https://ez.analog.com/message/294001?commentID=294001&et=watches.email.thread#comment-294001>
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Re: EVAL-21479-EZLITE USB inteface red in SigmaStudio for SHARC
Sharing the solution. The documentation is current....
You need EVAL-ADUSB2EBZ & ADZS-USBI2EZB to run the demo example.
EVAL-ADUSB2EBZ is an adapter used as an USB-to-SPI converter.This part is sometimes labelled as EVAL-ADUSB2Z.
ADZS-USBI2EZB is an adapter board used to connect EVAL-ADUSB2EBZ socket to the EZ-KIT Lite.
Please refer "Hardware Requirements" in attached Users guide.
In this guide USBi is referred as EVAL-ADUSB2EBZ not SADA board.
The SigmaStudio for SHARC demonstration setup includes a Host PC running SigmaStudio which is connected to the SHARC Target board. The connection is achieved using a USB-to-SPI converter. The ADZS-USBI2EZB acts as the USB-to-SPI converter, which is connected to the PC through a USB port and to the SHARC Target EZ-KIT through SPI lines.
Please refer "Demonstration setup" & "Connecting EVAL-ADUSB2EBZ to Target" in attached Users guide.
Regards,
Processor Tools Support
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AD5933 / AD5934 stuck in program-flow, DFT does not complete
Hello
i am using Ad5934 . i stuck at program flow at poll the status register(0x8f) to check wthere valid data is at present .status bit D1 should be set after start frequency sweep command but it not.. i have cheeked i2c write/read data is ok .
the flow of my program is
1.reset part
2.Program the start frequency
3.Program Δf
4.Program the number of increments
5.Program the delay in the measurements
6.Initialize the system & Wait few ms
7.Frequency sweep.
8 check status register ox8f ( i stuck at this place)
///// reset the part ///
i2c_write ( 0x81, 0x10);
Delay_ms(100);
// program 30khz start frequency assuming internal osc of 16.776Mhz
i2c_write ( 0x84, 0xC5);
i2c_write ( 0x83, 0xF3);
i2c_write ( 0x82, 0x00);
// program 10hz frequency increment assuming internal osc of 16.776Mhz
i2c_write ( 0x87, 0xE2);
i2c_write ( 0x86, 0x79);
i2c_write ( 0x85, 0x00);
Delay_ms(100);
// Transmit to NUMBER OF INCREMENTS =10 register
i2c_write ( 0x89, 0x0A);
i2c_write ( 0x88, 0x00);
Delay_ms(200);
// Transmit to settling time cycles register
// program 12output cycles at each frequency before a adc conversion
i2c_write ( 0x8B, 0x0C);
i2c_write ( 0x8A, 0x00);
// place the AD5934 in standby mode
// i2c_write ( 0x80, 0xB0);
// initialise the sensor with contents of start frequency regsister with range 1 (2vp-p, 1.6v) PGA = x1
status_register
Delay_ms(8000);
// start of frequency sweep (2vp-p, 1.6v) PGA = x1
i2c_write ( 0x80, 0x21);
Delay_ms(8000);
status_register = AD5934_Read(0x8F);
status_register = (status_register & 0x02);
while(!(status_register));
after step 2,3,4, i have checked the value of status register is =0x40; it is not changing after step 6 and 7 it remains 0x40 .
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Re: AD9508BCPZ-no output
Square wave 3.3 V (Schmitt trigger output) in single ended mode (without a capacitor, IN_SEL LOW) should work 100%, but it doesn't.
Are there any special requirements on voltage sequence of the Vdd, SYNC, etc.?
Could you review the connection? Could something create a problem?
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ADF4356 VCO core controlled by ADF4158
Hi,
I am planning to use ADF4356. My question is- Is it possible to control the VCO core externally by a different chip like ADF4158?
Looking forward to your reply.
Thanks
BR
Nikhil
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Re: AD5410 Iout Fault
Hi sonocide6,
- What SPI mode are you using in your uC? (what clock polarity and clock phase -CPOL & CPHA).
- Do you power your uC from the DVCC supply of the AD5421?
- Do you wait at least 40uS after your initial software reset before you communicate with the part again?
- What voltage do you measure at the REFOUT pin?
Can you share the full schematic and gerber files (you can private message your email address to myself or rrosario by clinking on our names above)
Regards
Michael.
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Two HMC7044 connection problem
Hi :
If HMC7044 can be used as HMC7043 fuction? i intend to use 2 pcs HMC7044 to generate 20 output clock , does all output phase can be remain unchanged before and after each boot ,I'm not going to modify the output configuration, I'm just worried about the different phases of the output on each boot.
i am debugging HMC7044 now, i found spur near the end of output signal , pls see the attached picture,i use ADM7150 as LDO and use nice reference signal , could you give me some advice about this issue?
Thanks.
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