Hi
Can I get the file with verilog?
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Re: Video with ADV7511 on the VC707
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Re: What is the typical noise figure of the HMC5805ALS6 @500MHz ?
Hi Antoine,
Please see attached.
Regards,
Sean
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Re: ADV7343 CVBS Output Distorted
Hi, as far as I know, IMX6 can directly output RGB signals. So that ADV7343 can be directly interfaced. If you need to feed 24-bit RGB signals to encoder, then timing mode 2 (slave) can be used in which the external VSYNC and HSYNC are generated by IMX6 parallel display output. But remember in 24 bit mode, you host should support dual clock mode where 2 clocks are required for 1 pixel as Anthony pointed out.
Anuradha
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Re: Measure conductivity below 25us with EVAL-CN0349 (AD5934)
hi glanthor: you changed the CN0349 calibration and feedback resistor, there have some rules should be following:
- the calibration resistor value should never small than feedback resistor, Rcal > Rfb must be always satisfied at any calibration point
- the conductivity cell resistance should be: Rcell > Rfb - R2
- all above rules is under the AD5934 transmit output at 1.98Vpp and PGA = 1, if you use other range or PGA setting, you need to calculate the limitation by yourself to make sure the ADC never overflow.
if you write the software by your self, I suggest you test the system from the low frequency side to void the stray capacitance introduced error.
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Re: ADA4930 oscillating with a feedback capacitor
Some more information about my observations:
1. No series resistor, no feedback capacitor, and no termination
(The picture below is a simulation that I try to build)
Gain and feedback resistor are 301 Ohm. The value of C1 here is a bit ridiculous. In real live it is more about 13pF.
Oscilloscope image
Ch1 yellow; input of the gain resistors (source V1 here). Active differential oscilloscope probe.
Ch 3 purple and Ch4 green; input of the single ended opamps that are not shown in the schematic above. I use a dual signal generator.
Ch2 blue; output of the differential opamp. As one can see it is not a nice sine wave. Active differential oscilloscope probe.
2.
Now the output series resistance is made 10 Ohm and parallel with C1 at the ADC input side a termination resistor of 100 Ohm is placed.
Channels same as oscilloscope picture above. Now the Blue is an almost perfect sine wave.
3.
Added 2x 3.3pF feedback capacitor in parallel with the 2 feedback resistors.
Now the blue output experiences oscillations. What is not wanted.
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Re: Analog accelerometer
Thank you so much, sorry for late reply. I actually checked the ADXL356 and its pretty good but I cannot find the data sheet of the evaluation kit. Where can I find that?
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What are the AD5060 command definitions?
Hello All,
Can someone tell me where to find the complete command definition information for the AD5060?
I do not see a table like that in the AD5064 datasheet.
Thanks In Advance,
John W.
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Re: ADIsimSRD version 2.0 - having issues with low modulation frequency support for ADF7020-1
I have exactly the same problem. There is no way I was able to make it work from 310-340 band and then get 155-170 by using the divide-by-2 option.
Then I cannot buy the capacitors, inductors and other components to populate the EVAL-ADF7020-ADBZ5 for producing 155-170 MHz.
Is there a way I can have help to finish my project and eventually go on production.
Thank you very much.
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Re: AD9874 EVAL-BOARD VCO
Hello,
Typically the AD9874 operates with a fixed IF (i.e. IF1) input frequency where its LO synthesizer is tuned to a specific frequency that results in high spurious free dynamic range in the passband region. Tuning the LO of the AD9874 over a wide 10-20 MHz range would not be advisable since one would be exposed to the various spurious issues such as the "image band" which is offset from IF1 by FCLK/4 (since IF2 internal to device is situated at FCLK/8). Perhaps for this reason.............it may be advantageous to 1st up convert the RF input (perhaps in 12-25 MHz range ) to a fixed higher IF1 (i.e. 140 MHz) with mixer and tunable LO where a SAW filter can then be used to remove out-of-band spurious.
One can inject an external LO into the AD9874 EVB to determine if an IF1=140 MHz remains clear of mixer spurious.
Lastly...............you may want just consider a high speed ADC like the AD9255 to digitize the 10-20 MHz spectrum and then use an FPGA to digital downconvert the desired target signal.
http://www.analog.com/en/products/analog-to-digital-converters/ad9255.html
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Re: ADXL362 data ready interrupt in stanby
Thanks for your question and sorry for the late reply due to the national holidays last week here in US.
After the ADXL362 entering the standby mode, all interrupts and data are preserved. This means you will see the data ready interrupt still there once you switch to the standby mode from measurement mode. However, reading any of the data registers will clear the data ready interrupt, even in standby mode.
Hope this helps.
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Re: DOES ADN4650 ISOLATOR must be inputted NRZ data?
Thank you for your inquiry. EngineerZone (ez.analog.com) offers support for English language inquiries only. You have two options for support:
- If you require assistance in Chinese please visit https://ezchina.analog.com/welcome.
- Post a NEW question in English.
This question has now been closed out.
Regards,
EZ Mgr.
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DOES ADN4650 ISOLATOR must be inputted NRZ data?
ADN4650 datasheet中提到了，其能接收600Mbps的NRZ数据，那么是否说，非NRZ的差分数据，这款芯片没法正常工作？
我们预期使用这款芯片进行视频数据的隔离。如果必须得是NRZ数据，那么这是由于icoupler技术本身的限制，还是别的？我看ADI这边像I2C ,SPI等的icoupler器件都可以的，没有说需要NRZ。望解答，多谢您；
The ADN4650/ADN4651/ADN4652 can operate with high
speed LVDS signals up to 300 MHz clock, or 600 Mbps nonreturn
to zero (NRZ) data.
speed LVDS signals up to 300 MHz clock, or 600 Mbps nonreturn
to zero (NRZ) data.
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Re: No output from ADAU1452 Master Control Port IO
Hello John,
Based on your earlier post on the 20th, I would say that all the Master Control Port cells do not function properly using SPI mode 0.
https://ez.analog.com/thread/100899-compile-error-adau1452-master-control-port-spi
I will be investigating this more in the coming days and will report this to the programming team. They did respond after your last post saying it would be fixed with the upcoming release. By any chance, have you tried this with the new Beta version that is up on the web? I will try it as soon as I have a moment to download it. I found the release notes to be useless and will report that as well.
Dave T
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AXI_DMAC Data Ready Interrupt?
We are using a picozed SDR SOM2 board with LINUX and designing our own FPGA. Right now, we are using the AXI DMA engine for the communication between FPGA and ARM CPU. For the DMA RX part, we only see two types of interrupts one for transaction pending and one for transaction complete. According to this Q&A https://ez.analog.com/message/324038-re-axidmac-how-to-configure-adcdma-trigger-interrupt-on-recieveing-data-block?comme… , Larx explained that the interrupt fires once all data has been captured. From what we observed, the transaction complete interrupt is for that purpose. But that requires ARM CPU to specify a data length before the actual communication. What if the ARM CPU does not know the data length before issuing the DMA transaction, but instead, waits for a data ready interrupt? Once the data ready interrupt is fired, ARM CPU then sends the RX transaction (with length specified) to the AXI DMA engine. We already implemented the FPGA part to inform ARM CPU about the data length. Can we piggyback the AXI_DMAC's interrupt for the data ready interrupt?
Thanks!
Guang
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Re: How to make two boards of ADS7-V2, with two AD916X Eval boards synchronized, assuming a single 2-Channel D/A, each channel at 12Gsps
I would recommend that you use the AD9172 Dual 12 GSPS DAC. It has an evaluation board that will connect to the ADS7-V2. As long as you don't need JESD lane rates above 12.5 GBPS, that eval solution should work for you.
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Re: AD9164 parameter
The AD9162 is a 6 GSPS, 16-bit RF DAC. With a special interpolating mode, called "FIR85 enabled", you can effectively run the DAC at 12 GSPS with the same 6 GHz input clock. So, if you ran the DAC at 4 GHz input clock and enabled the interpolating mode "FIR85 enabled", you would achieve an 8 GSPS DAC. You could use the AD9161 and achieve 11-bit resolution instead of the 16-bit resolution of the AD9162.
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Re: IIO crashes when callibrating for MCS using FMCOMMS5 board
Can you repost the error? Something didn't copy and paste correctly.
Also is OSC running on the board or remotely?
-Travis
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Re: CODEC chip ADAU1372/ADAU1777/ADAU1702 background noise problem
I'm moving this to the Audio community where someone may be able to answer your question.
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Re: How to get Simulink to work with Libiio ?
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Re: AXI_DMAC Data Ready Interrupt?
Thanks for the reply. By saying piggybacking, I mean the DMA IRQ can be reused. Can the DMA engine generate some interrupt when FPGA sends some data into the DMA engine?
Guang
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