HI
We are using six AD9953 DDS IC in our design. Each DDS IC is placed on seprate PCB board. Each board DDS has own Refernce clock (400 MHz). so is it possible to synchonize all the DDS by only providing coinicident sync clock(100 KHz) at sync_in pin and IO updates to DDS boards.
Thanks
Hi
I consider supply ICs for AD5422.(AVDD=15V,AVSS=-15V for 0-20mA,0-5V,0-10V)
AD5422 can set slew rate and some responses are required for supply ICs.
But I worry about cases required quick response ( AD5422 's On/OFF, reset ,etc)
How specification are required about supply IC.
regards
m-kun
Dear Jellenie,
it would be perfect if you can give me the gerber file.
Please send this to peter_m@sorabiabau.com.
BG Peter
Hello, I will use AD9653 (16 bit) to digitize 68Mhz carrier with 12.5Mhz Bandwidth. Which ADC driver is better to use with 0.9V ADC input common mode voltage and analog inputs matched to 50Ohm. I find ADA4930, but it's designed for "...driving 1.8 V high performance ADCs with resolutions up to 14 bits from dc to 70 MHz...". Can I drive differentially 50-Ohm matched ADC input by thic driver? Drivers which include internal resistive feedback such as ADL5562 has OP1db level in data sheet, how to find OP1db level for ADA4930 with external resistors? I want use driver with Vocm=0.9V and OP1db=15dBm ( 12dBm(2.6Vp-p@50Ohm) + 3db(Pdiff=Ps-e-3dB) ) to safe ADC input from 2.6Vp-p,max.
Dear Dave,
I read some more papers about our options and in my oppinion it could be the best option to directly go for the I2S interface. With the FPGA we are then more flexible to connect new sensors or actors because we can seperately add new features and don't need a complete audio codec with multiple IOs. In addition regarding signal integrity it is better to work with digital signals to avoid picking up RF interferences.
With the development of A2B it seems to be likely to work with digital sensors and actors. I couldn't find any hint on the internet regarding the prices of the AD2425, AD2422, AD2421. Are they already available? What do they cost? Are they capable to work with sampling rates of 8 kHz? Because we will probably work with 8 kHz. Therefore it would be best to work with I2S microphones, because they have the decimation filters already included.
We are looking forward for your feedback.
Best regards
Marc
Hi,
The AD9689/AD9208 evaluation board (SCH_9689ce02c.pdf) is designed to the Vita57.1 spec. But more importantly, it is designed to work with the ADS7-v2EBZ data capture board. The FPGA bin image is setup to use the connector J3 in the ADS7-v2EBZ as the REFCLK (GBTCLK) for the CDR within the FPGA's transceivers. The UCF can be modified to use any pins to get the REFCLK. The GLBLCLK is needed if you want to synchronize two AD9208-3000EBZ for example.
Thanks
Umesh
Hello,
I am using ADE7757 for my energy meter reading. So I got the data as mentioned below.
Load: 0 W
CF - 0 Hz
V1 - 25mV
V2 - 66mV
Load: 21 W
CF - 3 Hz
V1 - 25 mV
V2 - 66 mV
Load: 171 W
CF: 80Hz
V1: 24 mV
V2: 75 mV
SCF = 0 for all
S1,S2 = 1 for all
So How to calculate CF pulse in theory ? is this CF pulse is correct or not according to load ?
Hi epalaima
If internal pull-ups (PU) are included (see Pin Descriptions table in the datasheet), these pins can be left floating. This is the case for ADDR23–0, /MS0–1, /RD, /WR, ACK. Any pin that is output only can always be left floating, like is the case of the XTAL pin.
Now consider WDT and if not using in your system,
WDT_CLKIN (input)- This pin should be pulled low when not used.
WDT_CLKO (output) - Can be left floating
WDTRSTO (output) - There is an internal pull up resistor and can be left floating.
After reset, all ADDR pins are in external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default). /MS3 is multiplexed with FLAG3, which is an input after reset. FLAG 1 and 2 are also inputs after reset. If these pins are unused (for both flag and memory select functions), you can use a pull down resistor, assuming you are not changing their default stage (flag input).
BR,
Jithul
Ok, so the fact that the internal test pattern generator worked fine is a good sign that the encoder and its output circuitry is not the cause of the issue. By enabling/disabling the PLL, you have ruled out the possibility of noise interfering with the output through this avenue. Most likely the noise is coming in through the video pixel bus input from your processor.
Have you measured the video input bus for noise/jitter?
Register 0x88[5] gives a setting to reduce digital noise, have you tried toggling this? Does it have an effect on the video quality on your setup?
Best Regards,
Anthony
Hello
Any progress on this?
Regards,
Tomoto
Hi
Could I have your advise on this?
Regards,
Tomoto
I managed to set the desired signal to a high voltage state by controlling the axi_gpreg core from a linux application. Pin 1 of the fan plug (P3) is now at ~0V and pin 2 is at 4.9V. So far so good.
But when the fan is connected the voltage suddenly drops to ~1.6V and the fan stays off.
Does anybody have an idea what is going wrong and how to cope with this problem?
I appreciate any hint.
I'm also seeing phase variation with amplitude variation in between frames.
And If this IIO system object is not working properly, then what should I use for evaluation?
Hello Dave,
Perhaps a bit of a misunderstanding: we only have 1x evaluation board, together then with various revisions of our own custom product (i.e. DUT). I have confirmed that the EVM works fine as both transmitter and receiver to a DUT (same as with other 3rd party receivers/transmitters), but the problem is always related to 2x DUT's.
I can confirm the date of the EVM later today, but it dates from around 2010. The breaks are confirmed on DUT's with DSP's ordered from Avnet ranging between early 2014-2017.
Has there perhaps been a silicon revision? I still need to do the I2S-I2S experiment, but can also as an extreme test replace the DSP chip on our EVM with a new one to see if that causes breaks.
Regards,
Pierre
Thanks for the suggestion. I will try a 100 nsec pulse. Let you know once I try it.
Mark's 12-Nov-2017 reply has a link to a thread that answers the CFR2[9:8] topic. In summary:
CFR2[9:8] SYNC_OUT
======== =========
00 or 01 SYNC_IN
10 Logic 0
11 SYNC_OUT Generator
Unfortunately, the CFR2[9:8] functionality is not particularly clear in the AD9915 data sheet (see Figure 48 on page 34). First of all, the upper input of the mux corresponds to CFR2[9]=1 and the lower input corresponds to CFR2[9]=0. Furthermore, there is an AND gate (not shown) between the SYNC_OUT generator and the upper input to the mux. One of the inputs of the AND gate connects to the output of the SYNC_OUT generator, while the other input connects to CFR2[8]. The output of the AND gate connects to the upper input of the mux. Putting this all together yields the table above.
Hi,
Can you try the following I2C Writes to see if you can read back the BKSV value:
Then read the BKSV Registers in to see have the values been populated.
Best Regards,
Anthony
However Rev. D states :
http://www.analog.com/media/en/technical-documentation/data-sheets/ADV7611.pdf
Only BSWZ-P seems to be Non-HDCP, or is this an outdated rev ?
Anuradha
Hi Akira,
The datasheet should contain most of the information you need. Please let me know if you have questions on setting up a specific mode.
Judy
Hi Antoine,
The image should show up as an attachment, looking like this:
I can see and open the attachment, but perhaps there are some flaws in the EngineerZone interface that are making it inaccessible to you.
For that reason I will try this two other ways: 1) by directly inserting the plot as an image in this message and, 2) by sending the plot to your direct email address. Please let me know if you still can't access it.
Regards,
SMcBride
