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EVAL-ADUSB2Z and A²B in SigmaStudio

November 27, 2017, 1:15 am
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Hi all,

 

I have installed SigmaStudio 3.15. on Windows 7 Professional, as well as the necessary USBi Drivers. I created a new schematic with an Audio Host (ADAU1452), an A²B-Master and an A²B-Slave. The PC interacts with the EVAL-AD2410WDZ Board (which contains the ADAU1452 and A²B-Master) through an USBi Adapter (EVAL-ADUSB2Z) v. 1.3. After starting the Link-Compile-Download process, only the A²B-Master is discovered, but not the A²B-Slave.

 

However, when a colleague of mine tries the same with the same hardware but with an older version of SigmaStudio (3.11.) on Windows XP, everything works fine.

 

My questions are:

- Is maybe the EVAL-ADUSB2Z v. 1.3. not compatible with SigmaStudio 3.15?

- Do I need a newer version of this adapter board?

- Is a firmware update possible?

 

Thanks in advance.

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Re: AD9361 1R 1T configuratin through Linux

November 27, 2017, 1:16 am
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AD4505-4 single negative bias operation

November 27, 2017, 1:17 am
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Hey,

 

i am desgning a quad negative voltage control loop for 4 EMLs. Each EML can sink up to 30 mA of current and needs a tunable voltage from -0.5 to -5 (depends on temp, bias etc....). to make a long story short i need 4 tunable negative voltages each sinking up to 30mA of current. There is nothing standard on the market for this (at least i didnt find anything, would be glad to find out i am wrong), so i decided to use a DAC in series with the AD4505-4.

 

my questions is this: 

 

can i provide a single negative 5 volt bias for the AD4505-4, i.e. V+ at GND and V- at -5 V (supplied by a charge pump).

 

thanks, Gal

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Re: AD8436: several questions about deployment

November 27, 2017, 1:25 am
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JS, again, thank you very much, this is also useful.

 

So AD8436 is the way to go. I will try to get an eval board to evaluate how it will work on my design.

 

Best Regards.

 

Elder.

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Re: Why does my Simulink freeze when i run Fmcomms3 example models?

November 27, 2017, 1:26 am
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Thanks mate, 

 

I would appreciate it if you gave me a ping when you guys figure it out, meanwhile i will try installing windows 7 instead. 

 

Best regards, 

Samer Alshaer.

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Re: Settling time

November 27, 2017, 1:32 am
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The discontinuities appear because of the delays between consecutive calls of the step() function which gets called on the model's main loop. Because there's a single thread of execution, beyond a certain sampling rate it is impossible to compensate for these delays with buffering in hardware. To overcome this you need to implement a multi-threaded consumer mechanism using mex or the Parallel Computing Toolbox.

 

Regards,

Andrei

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output voltage tolerance calculation ADP1762-ADJ

November 27, 2017, 1:37 am
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Hello,

 

I would like use ADP1762 adjustable LDO.

My application needs power supply +0.975V +-0.025V (≙ accuracy 2.56%) at 1.7A.
Supply voltage tolerance sourced to LDO input is +1.8V +-0.1V.
Ambient temperature definition from 0°C to +40°C.

How I have to calculate LDO output voltage tolerance?
Is it possible to achieve requirement with ADP1762 adjustable device?
Do I need Radj with less then 1% tolererance?

My worst case tolerance calculation resulting in more then 4% exclusive Radj tolerance.

It seems to be unusual much.

 

Best regards
Andreas

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Re: Settling time

November 27, 2017, 1:42 am
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Here is my Matlab code:

 

s = iio_sys_obj_matlab; % Constructor
s.ip_address = '192.168.10.211';
s.dev_name = 'ad9364';
s.in_ch_no = 2;
s.out_ch_no = 2;
s.in_ch_size = 5000;
s.out_ch_size = 5000;

 

s = s.setupImpl();


input = cell(1, s.in_ch_no + length(s.iio_dev_cfg.cfg_ch));

 

itr=floor(800000/s.in_ch_size); // total sample size is 800000
inputdumr=cell(1,itr);
inputdumi=cell(1,itr);
input{s.in_ch_no+1} = 300e6; // Tx Lo
input{s.in_ch_no+2} = 300e6; // Rx LO
input{s.in_ch_no+3} = 'slow_attack';

 

 


output = cell(1, s.out_ch_no + length(s.iio_dev_cfg.mon_ch));


final_out1 = [];
az = load('FMTxout2.mat' );
final_out = az.final_out2;
final_in1=[];
final_in2=[];
for i = 1:itr
for j=1:s.in_ch_no
strt_idx = 1 + s.in_ch_size*(i-1);
end_idx = strt_idx + s.in_ch_size-1;
if j == 1
inputdumr{i} = 1024*real(final_out(strt_idx:end_idx)).';
final_in1=[final_in1;inputdumr{i}.'];
elseif j == 2
inputdumi{i} = 1024*imag(final_out(strt_idx:end_idx)).';
final_in2=[final_in2;inputdumi{i}.'];
end
end
end
for k = 1:itr
input{1}=inputdumr{k};
input{2}=inputdumi{k};
output = stepImpl(s, input); // step Impl call
out = (cell2mat(output(1)) + 1i*cell2mat(output(2)));
final_out1 = [final_out1;out];

end
rssi1 = output{s.out_ch_no+1};

save FMRxout.mat final_out1;
s.releaseImpl();
figure % new figure
ax1 = subplot(2,1,1); % top subplot
ax2 = subplot(2,1,2); % bottom subplot

plot(ax1,output{1});
title(ax1,'I');
xlabel('Sample');
ylabel('Amplitude');

plot(ax2,output{2});
title(ax2,'Q');
xlabel('Sample');
ylabel('Amplitude');

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Re: AD9361 1R 1T configuratin through Linux

November 27, 2017, 2:00 am
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   Thank you Dragos and Michael for the quick replies.

   I understand that,  1R 1T configuration can not be configured run time with the present boot image. While creating image I should have to incorporate a different .dts. I will communicate the same to our software team. Can you please suggest me if there is an pre-built image available with this configuration readily (just to cut down the waiting time for a new build)

 

Thanks,

 

Prasad

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Re: Settling time

November 27, 2017, 1:59 am
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ACozma wrote:

 

Right, so the bottleneck is the part where the stepImpl() function gets called. To make things truly efficient what happens in the stepImpl() function needs to go into mex code and there needs to be a proper producer/consumer threading implementation.

 

The example that we have now is store and forward, which means discontinuities between buffers. There's a plan to show continuous streaming but no defined schedule yet.

 

Regards,

Andrei

You said there is a plan to show continuous streaming. Is there any blogs explaining  it?

And My question is, are these discontinuities affecting the amplitude variation in between the frames eventhough I set my gain constant in gain table?

But I didn't see any amplitude variation in digital loopback.

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Re: ADF7242 stops generating Receive interrupt to Linux driver

November 27, 2017, 2:34 am
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When you hit this - is the IRQ strobe high or low?

Have you looked at the SPI strobes - especially the CLK close to the ADF7242.

Could it be that there is some over- or undershoot and that the 7242 sees an additional clock?

 

On my RaspberryPi setup I can't see any failures - and it's receiving millions of packets.

I know from the status - the device should generate an packet receive interrupt if it receives a valid packet that passes the frame filtering. Something on your end must be different. Let me see if I can setup a ZED board here.

 

-Michael 

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Re: AD9680 and Cyclone V Hardware starting point

November 27, 2017, 2:34 am
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Hi Umesh,

 

thanks for your answer  I've had a look in what is available and found some tools for possible evaluation. But due to a lack of knowledge in this field, i need your help for evaluation.

 

As I want to use Cyclone V FPGAs i've found this SOM Enclustra FPGA Solutions | Mercury+ SA2 Which comes with a lot of IOs and a Evaluation Board Enclustra FPGA Solutions | Mercury+ PE1-200/300/400  which comes with an HPC FMC connector in Version:

  • 1 × FMC HPC connector (PE1-300)

 

My target is to get the data from AD9680, store it and make post-processing on the pga, and then use this in my linux, running on the ARM A9 inside the Cyclone V.

 

I found some tools from Analog Devices using the Evaluation Kits like (  AD-FMCDAQ2-EBZ) but they use Xilinx Boards. 

 

Would it be possible to use the driver set ADI provides (like AD-FMCADC4-EBZ FMC Board [Analog Devices Wiki] ) and build it for the Cyclone V family? Did I understand it correctly that I should use your IPs (Generic AXI ADC IP core [Analog Devices Wiki] ), are they working in my case?

 

And would it be possible to use VisualAnalog or other Tools from ADI on my Eval-Board with HPC connector?

 

Best regards,

Nils

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IIO crashes when callibrating for MCS using FMCOMMS5 board

November 27, 2017, 2:37 am
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Whenever i am  trying to connect with FMCOMMS5 board using IIO and calibrating for MCS,ie,clicking the TX1B_A to RX1C_B or any of the five options, the IIO GUI crashes and the following error comes:

 

Please help me out with the same.

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Re: ADF7242 stops generating Receive interrupt to Linux driver

November 27, 2017, 2:42 am
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While we check the first part, this is what we have as hardware setup:

 

SPI lines <--> Microzed PMOD connector (connected directly to zynq PS MIO)

IRQ line --> FPGA (Zynq PL) --> processor (interrupt id in the device tree file has been updated accordingly.)

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Re: AD9364 AGC and signal strength

November 27, 2017, 2:42 am
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if you reduce the power by 10 dB are you seeing same issue.?

 

If signal is high you should see clipping of the signal and not steps like what you are seeing.  Try capturing RX data using IIO oscilloscope utility and cross check.

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Re: Settling time

November 27, 2017, 2:53 am
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I don't think there are any blogs explaining how to do this other than the libiio documentation and matlab mex documentation.

 

If the gain is constant there should not be amplitude variations because of the discontinuities.

 

Regards,

Andrei

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Re: AD-FMCDAQ2-EBZ

November 27, 2017, 2:53 am
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Re: Why does my Simulink freeze when i run Fmcomms3 example models?

November 27, 2017, 3:08 am
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I am sorry to bother you again. But i wish to know what is the optimal windows version to install and experiment with Libiio and what is the best architecture x64, X32 ?. 

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daq2 different TX/RX lane rate

November 27, 2017, 4:00 am
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Hello,

I made my own board from AD9144 and AD9680. I am using your fpga reference design (2016_R2 and no-os on ZC706) to generate and acquire data.

After modifying you reference design, I made the AD9144 (single link mode 2) works as:

  • data rate = 491.52Msps
  • 4 DACs @983.04Msps (interpolation x2)
  • 4 lanes @ 9830.4Gbps
  • Ref clock = 491.52MHz so DAC core works at 983.04MHz (from software)

 

ADC is giving me more trouble. If I use the design with Ref clock = 245.76MHz, I am able to get the data from the ADC but the DAC is not working. So I tried these 2 configurations with no success.

Configuration 1: I changed the RX DIV from 1 to 2 in util_adxcvr

  • data rate = 491.52Msps
  • 2 ADC @491.52Msps
  • 4 lanes @ 9830.4Mbps/2=4915.2Mbps
  • Ref clock = 491.52MHz so ADC should work at 491.52MHz (from software) but it is still at 983.04MHz, is it possible to have different lane rate between TX and RX?

Configuration 2: I changed the RX num of lane from 4 to 2 (RX DIV=1) in util_adxcvr and changed the ad9680 register

  • data rate = 491.52Msps
  • 2 ADC @491.52Msps
  • 2 lanes @ 9830.4Mbps
  • Ref clock = 491.52MHz  so ADC core works at 983.04MHz (from software) and I got 2 errors:
    • XCVR initialization failed!
    • jesd_status jesd_status: jesd reset not completed!
  • I thought it would be straight forward and will get 1 samples out of 2 that will be good.

 

Please, could you help to find the best path to follow.

 

Thank you for your help.

 

Best,

 

Chris

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Re: Why does my Simulink freeze when i run Fmcomms3 example models?

November 27, 2017, 4:21 am
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The optimal version would be Windows 7 x64.

 

Regards,

Andrei

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