Re: Download the .pdf of the ‘Developing Multiple-Input Multiple-Output...
Hi Nestor, The frequency match is unaffected by the calibration. The two devices should be within a few Hz of each other, worst case, when using internal LO. When using external LO the frequency will...
View ArticleRe: ADZS-ICE-100B and urjtag
yes, the ICE-100B cable is perfectly working with VisualDSP-v5unfortunately it is not working with urjtag, which is required by the OpenSource toolchain. I have to use the OpenSource's one instead of...
View ArticleRe: ADC_CLK/DAC_CLK, BB filters of AD9361
Please see https://ez.analog.com/message/153509#153509 for clock and data rate discussion. https://ez.analog.com/message/156058#156058 contains a discussion and information on filters and filter BW.
View ArticleADV7181D input color space selection
Paragraph 2.4.4 of the User's manual states that the component processor can accept YPbPr or RGB input formats. I have an RGB source (not graphics) in NTSC format with sync on green. Want to use...
View ArticleAnalog Audio Input Levels on ADV7850
The datasheet for the ADV7850 talks about support for a 2.8V rms audio input signal on page 28. In that same section it also says "The input level at the analog audio input pins on the ADV7850 is...
View ArticleRe: initialization and calibration of AD-FMCOMMS1-EBZ
Lars, Thanks for your answer and I have another question. 1- I have AD-FMCOMMS1-EBZ set up and running in a no-OS mode. I tried to load the DAC files that come with board ( QPSK, QAM, ...). The eye...
View ArticleRe: offset from ADA4528: datasheet pspice
Hi Emman, I developing a Lock-in amplifier. And I need an input amplifier for the small signals. I want to take several ADA4528 one after another to get a high gain. But first I want to simulate all....
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AD9361 Rx Channel Bandwidth
Can the 9361 channel BW be configured for 25kHz? What kind of performance degradation will I see and what are the main drivers for the degradation?
View ArticleRe: AD9361 REF_CLK
Hi Reinhard, Yes you are corect the Reference clock input signal level should be 1.3V as typical value. The datasheet does not specify a minimum value. Is this something you need to know? As a test,...
View ArticleRe: AD9361 Software
Is it possible to get a legacy version of said evaluation software? If not, what is the most direct replacement for it on the analog devices site (link please?). I'm looking for something that can...
View ArticleRe: ADA4092-4 differential input voltage
Hi Terumasa, With your set up conditions, it clearly violates the absolute max rating for the differential input voltage stated on the datasheets and we really do not recommend that. However, based on...
View Articlequestion about U-Boot and USB page
On the following page:bootloaders:u-boot:usb [Analog Devices Open Source| Mixed-signal and Digital Signal Processing ICs]it documents what u-boot looks like when a USB flash drive is connected. Is it...
View Articlepotential USB issue on BF526 EZ-Board with 2013R1 and 2014R1
When I program my BF526 EZ-Board with u-boot-bf526-ezbrd-spi-2012R2-RC3.ldr, the "usb start" command seems to...
View ArticleRe: potential USB issue on BF526 EZ-Board with 2013R1 and 2014R1
One more thing. 2011R1 seems to work also. -Matt
View ArticleRe: Porting of AD9361 to Altera FPGA
Hi Brian, Actually the project seems to be fully functional (even if there were not tested yet all the aspects). It was created a wiki page where we will post some instructions: Altera SOC Quick Start...
View ArticleRe: ADV7619 HDMI Compliance Jitter Test 8-7 Fails
Hi Chris, We actually tested the EVAL-ADV7619-7511 board today in our pre-compliance certification lab in Japan and it passed. I will send you an email shortly on regarding ordering this. For your...
View ArticleRe: Zedboard and Fmcomms1 Reference Design
Thank you larsc. I followed your instructions by building the kernel and the devicetree, and the design is up and running! I have an additional question. I noticed that in the original design and the...
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Re: unstable video output from adv7850 when doing VGA 1600x1200 60hz
Jitter on VSYNC should not cause any issue, Same for HSYNC. If I recall correctly H_SYNC_LOCKED is based on counting 8 lines worth of pixels and then there's a threshold difference there before...
View ArticleDifference of ADV8003/5 schematics
Hi, If shift ADV8003 project to ADV8005.Except Pin AA8(DDR_A[13] ) as datasheet description,Have any difference of ADV8003/5 should to change?Thanks,Kevin
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