Hello Paul,
Reading the AN-1061 attentively, I understood a non-controlling nature of the phase and frequency lock detectors. In my opinion frequency and phase locks are not threshold states such as they are in analog PLL. They are defined by current jitter value exclusively.
Am I right?
Shall I set the DPLL loop filter more accurately to decrease the final jitter without changing TCXO for a while? By what criteria should I be guided during this setting?
Or must I change any other settings?
Best regards,
Ignat.