Hello, am an designing high speed spectrometer with ADSP-21489 running at 450MHz.
Detector is read by 16b 30MSps ADC with 128 words long bursts. Data from ADC is placed to 128 words long FIFO. FIFO itself has only 3 connections to DSP, FIFO_READ, FIFO_EMPTY, and FIFO_DATA[15..0] ( other FIFO port for loading data is handled by FPGA, so only 128 words will be placed inside FIFO when i receive trigger from laser
So read process would be wait while FIFO_EMPTY is low, indicating that data is not present inside FIFO, and when FIFO_EMPTY goes high, generate rising edge to load data to FIFO_DATA[15..0] . When wait few cycles for data to settle inside bus, and read it to internal dsp registers
Any idea how to read data to internal DSP registers ? since ADSP-2148 don't have any signal that can be used as FIFO_READ (Or FIFO CLK, you name it)
Since i have all AMI interface connected to FPGA, i can create signals i want. For now idea is this, AMI_MS pin and AMI_ACK will be AND"ed to get inactive signal, and CLK signal from DSP will be connected to counter. Output from AMI_MS and AMI_ACK "AND" operation will be used as reset signal for counter, and simple compare function will generate rising edge when enough rising edges was counted by counter. Question is when DSP will load data to internal registers ? i don't understand relationship between when CS is low, and when data is loaded when AMI_ACK goes high
