Thanks for the input Yagami.
But there is a bit more treachery a foot here..
Here's a quick road map:
DSP1:
BLCK0/RLCLK0 -> BLCK2/RLCLK2 : I2S Input From Digital Input Board ( DIX9211 )
BLCK3/RLCLK3 -> BLCK5/RLCLK5 : I2S Input From DSP2
BLCK6/RLCLK6 -> BLCK8/RLCLK8 : I2S Output To DSP2
BLCK9/RLCLK9 -> BLCK11/RLCLK11 : I2S to Digital Output Board ( DIT4192 )
DSP2:
BLCK0/RLCLK0 -> BLCK2/RLCLK2 : I2S Input From Digital Input Board ( DIX9211 )
BLCK3/RLCLK3 -> BLCK5/RLCLK5 : I2S Input From DSP1
BLCK6/RLCLK6 -> BLCK8/RLCLK8 : I2S Output To DSP1
BLCK9/RLCLK9 -> BLCK11/RLCLK11 : I2S to Digital Output Board ( DIT4192 )
DSP1 -> DAC1: SDATA0 - SDATA4
DSP2 -> DAC1: SDATA0 - SDATA4
DSP1 -> DAC2: SDATA5 - SDATA8
DSP2 -> DAC2: SDATA5 - SDATA8
Clocks to the DAC's will be supplied from a single LMK00334 Fan out buffer which in turn will be fed from a Crystek CCHD957 ( 12.288MHz - Not listed but a custom ). Each DAC will feed the clock to its subsequent DAC.
Again, I'm not worried about the hardware as much I'm worried about the software 
My main concern is the I2C boot of multiple processors from a single MCU.
Along with separate Register Information and Settings for each individual one is what I'm confused about.
Slave Addressing will be as follows:
DAC1 - 0x04 ( ADDR1 - 0, ADDR0 - 0)
DAC2 - 0x24 ( ADDR1 - 0, ADDR0 - 1)
DSP1 - 0x70 ( ADDR1 - 0, ADDR0 - 0, Read/Write 0)
DSP2 - 0x72 ( ADDR1 - 0, ADDR0 - 1, Read/Write 1)