The FMC_TO_CPLD lines are going from the FPGA to the CPLD at Vadj voltage.
Inside the CPLD we are doign the SPI logic which controls the rest of the board at a known voltage (1.8 or 3.3,...)
to be able t ounderstand what is going on, I would say you should look at he HDL code and the drivers.
If you just want to run the demo, you should be all set if you downloand the software as is.
I hope this helps.
Charly