Hi all,
Please advise to us.
In the datasheet @ HMC835LP6GE,
1.2.1.4.4 VCO AutoCal Time & Accuracy, page 24,
Tcal = k128TFSM + 6TPD 2n + 7 · 20TFSM (EQ 7)
Tcal = Txtal (6R · 2n + (140+(3 · 128)) · 2m) (EQ 8)
What is the "k" ?
We can not understand equivalently equivalently (EQ 7) and (EQ 8).
Best regards,
sss
Hi aar0n,
Correct me if my interpretation of DIN is correct.
DIN: 0xAD 0xFF 0xFF
You should set the MSB (DB23) to logic "0" when you are not in toggle mode.
Can you try sending the sequence below?
DIN: 0x00 0xFF 0xFF
This should set VOUT0 to full scale.
Best regards,
Rainier
Hello Steve,
> Can you tell me how long you are waiting for the AD9545 to achieve PLD?
In the following case, about two minutes is needed to achieve FLD and PLD.
The "Freq Lock Tab Value" and "Phase Lock Tab Value" were increasing as same value.
1. SYS-IN : 61.44MHz from AD9520
2. REFA : 10MHz from N5181A reference output and AuxDPLL use REFA
3. SYS-IN and REFA and REFBB were inputed signals each before executing configuration the AD9545.
4. Execute configuration to AD9545
6. Wait for FLD and PLD
> Have you used the Fast Acquisition feature?
Yes, I used Fast Acquisition, but I don't know the setting is properly or not.
I would like to lean about the parameters.
> On the ACE software, can you do a "Read All" and then save the .cso file and post it here?
Please check attached file.
I would appreciate it if you give me some advice for appropriate setting.
By the way, still I can not affect fill rate and drain rate to increase Tab Value.
I'd like to short the locking time , so I set 0x64 to 0x0803/0x0804/0x0808/0x0809.
But the increasing and Decreasing step is still 10(0x0A).
Two minutes of locking time will be too long for our customer especially for Unlocking time.
Could you please advise to me how to change the step rate in increasing Tav Value ?
Best regards,
ysuzuki
Hi,Hfuhrhurr
Thankful for your reply
My MCU control the reset pin of ADSP21489 for low (wait more than 200ms),then this control IO Pin become to High,
After that ,this Pin (set it to input mode) to monitor the ADSP21489's Reset pin wait the high level ,when mcu get high ,it begin to send ldr file (slave boot ldr ) to dsp for boot. i donot know which part i did it error??
this problem have troble me for two weeks, I have to give up for it,
I will change the boot configre pin to SPI master boot
Hi
Thanks for reply,
I found my monitor from the 8005 EVA board cannot support 10bit, 12 bit color deep.
After change another monitor, it's OK.
I check the 7625 & 8005 register, it get correct color deep setting for 10 bit, 12 bit input signal.
Thanks
Ken
Hello,
I've been using ADF4360-7 in several designs . .
The ref frequency is a 16.368MHz crystal. ADIsimPLL was used for the design of a fixed frequency output of 398.98MHZ. Power supply is 3.2V well regulated. Nominal settings are:
C reg: 0x004FC520
N reg: 0x0261622
R reg: 0x00300FFD
L1 and L2 are 22nH shunted with 470 Ohm resistor.
The same design works in other boards but I am unable to get it to lock in the current board.
On checking the cp pin out im getting a square wave of frequency 8khz.Im debugging the issue from two months.
can u plz tell me what may be the issue and wt could be done to solve it??
Hi Community team,
I construct a simple flowgraph that save real and imaginary data from a signal source. The flowgraph is QT GUI with amplitude set to 0.5 and frequency is 1000 as shown in figure below. Then I verify the data from .dat files by run python scripts and show similar and consistent value what I expected. Where I can calculate magnitude is ~0.5.
Then I added FMCOMMS2 source / sink into same flowgraph as shown in figure below. I did a similar verification process. I found that the result is wrong. I believe the Head block is the root cause , but if i removed this Head block, I will get/ need to process a huge amount of .dat file generated ( xxMByte).
Then I verify again using Time Sink after FMCOMMS2 Source ( remove head block ), the waveform is look good with magnitude ~0.5.
My aim is to get correct data in real.dat and imaginary.dat after add FMCOMMS2 blocks / Head block. Any one have some idea how to solve this issue?
Thank you
The problem with that is the drawing looks like the ADC uses the output of the buffer which is the REFCOMP net. In the datasheet, it says the amp gains 2.5V by 1.638 to get a voltage of 4.096 on the REFCOMP pin which, from all the diagrams in the datasheet, look like that is what is actually bias'ing the ADC. Could you elaborate on why this isn't the case?
Also, the data sheet says that I can ground Vref and drive REFCOMP with a new biasing voltage. I need to bias this ADC at 5V. If I ground Vref and drive REFCOMP with 5.00V (from a voltage ref.) should this part work? From the data sheet, it looks like it should but I'm unable to get the device to work properly. I have a 10uF and 0.1uF in parallel on the REFCOMP pin as well.
Thanks!
Hello Dragos,
we have already downloaded kernel driver, but we want to use our own application in user space. somewhere it is mention that its is possible with libiio and uio. that we know,
can you please provide us direction to use our own application in the user space, we have our own DMA to transfer the data to FPGA from ARM, only we want to control AD9361 through SPI and IP core in FPGA so, how to access SPI and IP Core function in linux driver and integrate with our own application.
-Narendra
On chip mixers cannot be bypassed. You can look for direct RF ADC/DAC which suits your application and BW.
No, only one of those is supposed to do the job: either the 100 Ohm resistor or the shubber, not together. The suspicion is that neither will help much as the culprit seems to be that high frequency "bumps", not the transition between the steps. Therefore, not much point trying 10 Ohm, etc.
If you are ok cutting the traces, the next to cut is the one running between the "+IN A" pin and R1/R5/C1 node. Insert a resistor R between the "+IN A" pin and R1/R5/C1 node and a capacitor C between the "+IN A" pin and ground forming an RC divider, which acts as a low-pass filter, something like the one shown here. There is a formula for fc: "corner" or "cut-off" frequency as a function of R*C, so you can pick some R and C values so that the frequency fc is something like 10-15 KHz: substantially higher than your working frequency, but much lower than the frequency of those parasitic "bumps". R = 10k and C = 1nF would be a good choice (the connection between “-IN A” and “OUT A” should be restored, obviously).
If this does not work, there may be some issues with ground loops, with the power source, interference from the digital lines, etc. which are really hard to debug and virtually impossible to deal with remotely. Good luck.
Analog filter BW is decided by the actual BB BW requirement.
The roll-off in analog is compensated in digital while generating FIR co-efficient, this is the reason we recommend to use profile generator. Also profile generator will take care of all the internal clock dividers and ADC related config.
Hi,
I enabled every measurement mode, Full bandwidth mesurement mode, Instant on mode and Wake up mode, in the POWER_CTL registor but the situation remain unchanged. I could get only all "0" in MAXPEAK registors "0x15" to "0x1A". Do you have any sample program becomes helpful in setting and reading for the peak detection?
Regards,
Kazu
Changing FPS also changes the pixel clock, without Frame Buffer that's not possible.
If you want to change the FPS, it has to utilize Frame Buffer, but ADV7611 doesn't have a frame buffer, so you can't.
You need an FPGA after ADV7611 to convert the resolution.
For example, CYCLONE V + VIP Suite Scaler
Hi,
Thanks for your help. There is one more thing i would like to know. What exactly is the function of V_FREQ[2:0]? Does it set the vertical frequency of the output video or does it specify the vertical frequency of incoming video?
I tried whatever you instructed,
And now run that program as mentioned in the link: https://github.com/analogdevicesinc/linux_image_ADI-scripts/blob/master/test_tx_fastlock_pinctrl.sh
I just added one line at the end of the final for loop which will show the TX-LO frequency.
And this is the response I got:
If you see here in this program, the profile no.0 is explicitly recalled so the LO frequency is settled to 240MHz (pointed by profile 0) but after that the transitions in CTRL_IN pins has no effect on LO Frequency.
what is the problem here? Do I need to set any other parameters?
I think @vrsauce wants an HDMI 2.0 Receiver recommendation, not HDMI to LVDS conversion.
Hi,
We're using ADSP-21488 in one of our products. We wanted this processor to boot from the Flash. In our prototype board we connected the SPI lines as follows:
DPI_P01 -> SPI0_MISO
DPI_P02 -> SPI0_CLK
DPI_P03 -> SPI0_MOSI
We made sure that the flash has the right content (proper loader), but the DSP was not booting from the flash. When we probed the SPI lines while powering-up, we found out that the SPI clock is appearing on DPI_P03. In the hardware reference manual we found out that the default routing is as follows:
DPI_P01 -> SPI0_MOSI
DPI_P02 -> SPI0_MISO
DPI_P03 -> SPI0_CLK
Does this mean that the DSP bootloader expects this routing while booting up ?
If that's the case, how do we change the bootloader code such that we can map our hardware routing and reprogram the bootloader ? (Changing the hardware connections at this moment is very difficult. So, we are looking for a software solution!)
Expecting a reply soon,
Thanks,
Aswin
Hi, I am developing a waveform acquisition system using AD9689-2600EBZ and a FPGA board. Succeeded in capturing ADC data at 2 GS/s over JESD204B. Basically it works. But the ADC data looks noisy for a while after initialization of AD9689 registers. Noise level decreases with time, and disappears after a minute. See attached picture.
It depends on initialization of the registers, not power cycle. Instead of ADC data, I tried out generating ramp data in test mode of AD9689 (register 0x0550). There are no noises in that case. So the noise seems to come from the ADC core.
I am thinking about waiting for 2 minutes, like a warm-up time.
Any ideas to eliminate the warm-up time?
Thanks,
--fuji