hi:
I also found this problem when i test ad9361 at 2R2T, LVDS, FDD MODE, under 50m sample rate .
AD9361 input signal from signal source,freq 2537MHz,AD9361 rcv lo is 2536MHz.I get rcv signals from ad9361,then anlyse them used by fft.I found the mirror frequency at -1MHz lower 10db,compare to 1MHz.
when i delay q by one sample point,the mirror frequency disappeared.
Hello team,
We are waiting for your reply. It is urgent as we are working on our custom board. We are under great stress.
Please help us
Thanks
Abhishek
Hi Dg@4,
Our meter should work all the time for energy accumulation, then you will get the real value. We assume the waveform is good enough in reality, actually it's hard to find the absolutely zero crossing point of the waveform in reality, what we can do is try chip's best to get the most close point and get the value. When you get the energy value in first zero crossing point, more or less time, and the next accumulation will add more or less energy, so in a long time, the error can be very little.
Best regards,
Gary
Hi beelinic,
It is possible if both clocks are synchronized to each other all the time. But better to use two optical fibers for MCLKIN and MDAT and observe the timing diagram shown in FIgure 2 in Datasheet.
Regards,
Daryl
can you please suggest me any IC to meet my requirements... 40channels of adc with 16bitdata, min 250ksps speed and need synchronization on 3 IC's(if consider AD7616)
Refer BIST doc for details
Hi,
Similar issue reported on using FTP. Please follow the procedure said in this thread adv7401 register configuration software (copied below for reference). I believe this would resolve your problem.
Change FileZilla Site Manager -> General tab -> Encryption from "Use explicit FTP over TLS if available" to
"Only use plain FTP (insecure)" allows FileZilla to work with our FTP server.
Thanks,
Poornima
Same discussion is followed in below post
Refer UG-570 page 12 for calibration time for RF DC offset calibration.
There is no API available to disable power only to RX path.
Refer data sheet for current consumption for various modes to calculate power saving.
Yes TX path will still work.
If you want TX only - Why not enable TDD mode and set ENSM mode to TX?
This will effectively power down the entire RX chain.
If you need to turn off the TX LO while in FDD mode.
You can use this: Local Oscillator Power-down
-Michael
Hi,
Do you have one of our evaluation board for ADV8005?
How do you configure the board either through script or through software driver?
I believe ADV8005 data input will support both non deep color modes(8-bits per channel) as well as the deep color mode(30, 36 and 48 bits respectively)
Based on the arrival of the data,the Video FIFO block will unpack the input data,but it is not specific to 8 bit mode input.
Thanks,
Poornima
where i can find a hdl reference design for AD9171-fmc-EBZ or equivalent that can work with it
Hi Micheal,
Just a little information from you, what is the GPIO pin number for control input(ctrl_in) pin?
Is it no. 43,42,41 and 40?( which will be 97,96,95 and 94 when added with default no.54 while exporting)
So what you trying to say is that if there is any error(Due to wrong detection of zero crossing resulting in less or more time) in energy accumulation in say third cycle then that error will be compensated in the fourth cycle.
You really need not to call this function directly. MYKONOS_getInitCalStatus will provide you the required details. Alternatively you can call MYKONOS_abortInitCals to get the list of cals completed in last MYKONOS_runInitCals call.
Let me know if you still need more information.
Yes -
CTRL0 will be 40 + 54 = 94
94 + 906 = 1000
root@analog:~# cd /sys/class/gpio/
root@analog:/sys/class/gpio# ls
export gpiochip890 gpiochip906 unexport
root@analog:/sys/class/gpio# echo 1000 > export
root@analog:/sys/class/gpio# ls
export gpio1000 gpiochip890 gpiochip906 unexport
root@analog:/sys/class/gpio# echo high > gpio1000/direction
root@analog:/sys/class/gpio# echo low > gpio1000/direction
-Michael
Hi,
In the table 1 of AD9106 Rev C datasheet the FSO current @3.3V is specified between 2mA and 8mA with a "typical" value of 4mA. The note (1) adds that these values are based on Rset = 8k.
Does this mean that I can obtain from 2 to 8mA IoutFS if Rset = 8k, due to a poor accuracy before calibration?
Or does this mean that - with a 1.0V Vrefio - 8k gives 4mA, but IoutFS won't go under 2mA even if DACxRSET contains less than 0x05 and won't go over 8mA even if DACxRSET contains more than 0x14?
(I found the answer that explain DACxRSET is 0x0A at reset, which gives 800 Ohms x 10 = 8000 Ohms, hence through equations (3) and (4): IoutFS = 32 x 1.0 / 8000 = 4mA.)
Thanks.
Thank you very much!!
SO ,this mapping of 4 control input(CTRL_IN) pins are correct.
CTRL_IN0 = 1000
CTRL_IN1 = 1001
CTRL_IN2 = 1002
CTRL_IN3 = 1003
Hello,
We are working on No-OS driver over ADRV9361.
We need to perform a frequency offset corretion over temperature variations, but, because ADRV9361 uses an oscillator, DCXO tune features can't be used.
What is the best way to do this compensation?
Many thanks