After I press save settings, all the AD9361's settings have changed.
Firstly,I'm not changed the parameter of the settings of the FMComms2/3/4/5 Advanced. I just push the save settings(Experiment with what changes)
Then,Many of the features are wrong.For example,I can't connection with the IIO Oscilloscope.
I can't remotely connect the simulink module in real time.Beofore I press save settings.Everything is OK.
I want to know how can I revert to the previous settings.Thank you!
I downloaded the High - Speed DAC Software Suite.
And I pulled out the schematic from a lot of data and offered it to my customers.
Thank you very much.
thanks!
Before I use win32 write the image.I also have use win32 generate MD5 check code.it's matched with the official MD5.Then I write the image to my new SD card.
Hi,
The IP2 is not a standard test parameter for our RF switch products, so we don't have IP2 test data available for ADRF5020.
Best.
Hi,
IP2 is not a standard test parameter for our RF switch products, so we don't have IP2 test data available for ADRF5250.
Best.
You said "If you are sending it a BCLK that is 6.144 MHz and you are not getting proper out of the DAC then I signal it is not that designed.MHz BCLK with 64 transitions per frame. "
This is the customer's design intact.
This design is dedicated to the AD 1852 and well verified by customers.
This design is working properly.
We were convinced that the format and signal of the design were correct.
I will report that the customer gave up pursuit of failure and decided to proceed with the newly designed design.
Thank you for your support.
Thank you very much.
Oh, Kris, excuse me, forgot to mention:
The Hold-capacitor is 120pF, the filter cap C265a will be 33pF.
4k is the output-resistance of the Integrator, preliminary to the Sample-and-Hold, so feeding the Inverting Input of the OpAmp via a CMOS switch
Met vriendelijke groet / Kind regards,
Hans Splinter
Technical Sales Engineer
Phone Direct +31 6 2280 4256
Fax +31 26 365 2254
Mobile +31 6 2280 4256
E-mail h.splinter@solarnederland.nl<mailto:h.splinter@solarnederland.nl>
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Solar Nederland B.V.
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Phone 088-7652700
There should be a folder on the FAT partition called zynq-common.
Copy uImage to the root of the partition.
-Michael
Hi ADI Expert,
Can you please kindly share the gerber file of ADP5080 to me? Thanks!!
And I have some questions about ADP5080's spec, can you please kindly help to answer my questions as below :
1. CLKO is the internal switching clock used for Channel 1,
What's the function of this pin usually be used for? Can we provide this frequency to another device ?
2. EN pin's maximum VIH (EN) is 2.15V, can I control this enable pin if my controller I2C interface is 1.8V IO voltage domain? And why EN34 pin's maximum VIH (EN) is different from EN pin?
3. How would you suggest us to set's Charge Pump output voltage for best efficiency if only use for driving FETs?
4. Do we have tool to simulate if we all use 2.2uH conductor at output side?
5. Can we disable LDO1 & LDO2? If yes, how's the Iq when LDO1/LDO2 are both disable and EN is low?
6. Can we use Channel 7 LDO with 10V/35mA if I adjust current limit higher?
Look forward to your kindly feedback!
Henry Tang
Hi, Dalu,
The exposed pad is internally connected to pin 2 & 15, as described on p. 6 of the datasheet. The exposed pad would best be connected with vias to a large pad on the opposite side of the pcb (yet separate from the 0 V Ground in a dual supply system) for thermal dissipation. More importantly, the logic levels are referenced to the -2.5 V supply, and they still need to meet the corresponding Vih and Vil threshold requirements for proper operation. Comparators with open-drained outputs may be needed to shift the normal logic levels (say, 0 to 3.3 V) to this shifted range of
Vih > 1.8 - 2.5 V, i.e., (-0.7 V to 2.5 V)
Vil < 0.8 - 2.5 V, i.e., (-2.5 V to -1.7 V)
Benjamin
About question (5).
I never saw Hilbert transform as built-in function in SDR. You don't need Hilbert transform because you can work with complex signals. Hilbert transform is useful for RX part when you use single ADC (real signal) and don't have complex signal. But PlutoSDR has complex DAC (I and Q) and complex ADC (I and Q). I don't see why you may need Hilbert transform for PlutoSDR.
Danil Shendrik, IPrium LLC
Hi,
Please refer ADV7625 register control manual page no:190 which is available at ADV7625 Design Support Files
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Best Regards,
Jeyasudha.M
Basic requirement is for a 6 bit linear attenuator. Is this possible?
Hi,
Of course, I know that.
Please read the questions carefully.
Then please proceed to the next stage.
Best regards,
Hello everyone,
I have searched the related question in the forum, and I found this topic:
Bob gave the answer, but I still have some questions about the "Hilbert Transform" (I can not fine the answer from the wiki, because the page is gone.)
About the Hilbert Transform,
The upside output is 0 degree or 90 degree?
from the Bob's answer, this implement 350 degree adjustable, if I only want to adjust 0 to 180 degree from the ADC, how should I do? change the sine and cosine LUT table? and how to make a step, like 0, 10, 20, ....., 180 degree
Please help me for the question,
Thanks!
Alvis.
Hi,
Below is our suggested driver circuit that enables the use of positive logic voltages (TTL or CMOS) to control the switches like HMC547ALC3 that require negative control voltages (0/-5V).
The inverters of this driver circuit require negative supply voltage of -5V.
If there is +5V available in the system, a voltage inverter (ADM8828/ADM8829 or similar) can be used to generate -5V.
If the positive supply available in the system is not equal to 5V, a voltage converter (ADM660/ADM88660 or similar) can be used to generate -5V.
Best.
Hello.
I want to know AD9162 JESD204B SYSREF Function.
There is a variation in the phase relationship between SYSREF and DACCLK when
JESD 204 B is operated in subclass 1. If it can not meet the setup hold time standard of
SYSREF described in datasheet 9 page, I think that the link of JESD204B will be broken.
Is there a status that alerts AD9162 that the link has expired or that it can not afford the setup hold time?
Or is there a function or setting that corrects the phase variation of SYSREF?
I would like to confirm these two things, please tell me about the following contents.
1.
When I tried turning off the input of SYSREF when it operated without any problem,
the status of register 0x024 changed from 0x00 to 0x18.
Is it okay to recognize that bit 4 IRQ_SYSREF_JITTER on the datasheet page 84 will become '1'
unless it meets the SYSREF setup hold time standard?
Or, because there is no margin to the standard, will it be '1' when the phase adjustment of SYSREF
is necessary?
Also, at what point will IRQ_DATA_READY of bit 3 become '1'?
2.
A description of SYSREF synchronization such as IRQ_SYSREF_JITTER is described
on page 54 and it is recommended to set SYSREF_JITTER_WINDOW of register 0x039 to
a minimum of 4 DAC CLK cycles, but what is this setting like?
For example, if you set 0x04 in the recommended 4DACCLK cycle, it can adjust the setup time
of SYSREF within the time of 4DACCLK cycles, so it will be enough for setup time, or at least
4 DACCLK cycles, SYSREF I think that it is either the necessity of Hi time from the rising edge
to the falling edge.
3.
Please tell us about the following registers in relation to ② contents.
Registers 0x038, 0x37 SYSREF_PHASE 1, 0
Is it a status that can be used to adjust the phase on the data sending side (FPGA)
when using multiple DACs?
In that case, does it need it when using with a single DAC?
Or can it adjust the phase of received SYSREF?
best regards.
Hi,
The HMC435A has no integrated logic driver on the control ports. Control ports are directly connected to the gate of internal series and shunt switching FETs so the applied control voltages directly affect the RF performances, especially large signal performances (P1dB and IP3). We recommend a tight tolerance of +/-0.2V on the control voltage level (Vctl=0/+5V) for minimal performance variation from datasheet specs.
Best.
From the code above I can see input{s.in_ch_no+3} = 'slow_attack';
To have constant gain the gain mode must be set like this:
input{s.in_ch_no+4} = 'manual';
input{s.in_ch_no+5} = 0; % set this to the value that fits your amplitude requirements
IIOD with USB support applies to the systems that have USB connection. This is another backend supported by libiio, but it will not affect the discontinuities in between frames.
To get continuous data the only solutions are to implement in MATLAB the consumer model suggested in the previous answers, or to implement your own multi-threaded C application.
Regards,
Andrei