Hi,
1. That’s right, Figure 5 on page 9 follows the falling edge of CS on Figure 2 on page 8 of the AD7607 datasheet.
2. By stopping reading, do you mean not issuing a RD/CS pulse to the part? Applying a sequence of RD pulses to the RD pin of the AD7607 clocks the conversion results out from each channel onto the parallel output bus, DB[15:0], in ascending order.
For your other questions earlier,
3. The feedback resistor varies dependent on the range – it scales the bipolar signal into a 0-5V signal for the ADC
4. The group delay is the delay seen on the input signal as it passes through the PGA and the AA filter on the AD7607. For a given input frequency, there will be a group delay. The plot on Figure 34 shows the group delay vs input frequency.
Regards,
Karen