bro for some reason i cant get the edk design to run,after i am done generating .ngc files and .v files using coregen and copying them to their corresponding folders,the design builds smoothly but in sdk after the fpga is done being programmed with the bit file,i run the elf.the sdk gives the error that microblaze is under reset...i tried connecting to mb mdm but it says cant find an mdm module in hardware whereas there is an mdm in my hardware...i sought help and found out that the latest design works fine which is made in xilinx 14.6....i have 14.4....i tried downloading from xilinx website but i am unable to do it....it says you cannot download from the site right now...write an email to webmaster@xilinx.com....i have seen the clock syncs on oscilloscope using SMB to BNC connectors on hardware and it looks fine.....i have a suggestion for you...keep the ADC sampling rate as a multiple of LO frequency of 122.8 Mhz...then your system should work fine....is your LUT dac_dma_setup() output on ADC looking fine?..mine is showing a little bit of noise in phase and amplitude...i mean its not as smooth as the output of DDS.....but today i got a little better results and now i am very close to where i want to be...
i have a suggestion for you though
its not documented but i believe that when you try changing the dac sampling rate,the IP core 9122 starts operating at that frequency too and therefore you see the ouput to be multiplied or divided accordingly,keep the dac and adc frequency to be a natural number multiple of the LO frequency as the hardware can then interpolate or decimate the LO frequency to match your requirements,
so your output is in compliance with the system design and not anomalous,
i would however really appreciate if you can help me solve my problem too
best regards
ali malik