Dear Harris:
I have question when I used the AD9643 + ADC-HSC-EVALCZ ,
1. Setup:
HW
- Use AD9643 EVB + HSC-ADC-EVALCZ (FPGA)
- Use J506 default input path:
- Put C532, C533 0.1uF Cap.
- Remove the R541 & R542 Res.
- Input 50MHz on the J506 as clock input.
- Let AD9643 Analog input open.
2. SW: Use Visual Analog, Select FFT template.
However, it only can get about in-band noise about -47dBFS. It is too high.
Could you help check what's wrong on my setup?
Thanks for your help!
Cien