I've been attempting this code, however it always seems to provide syntax errors. I've tried converting the values using "16'h" for Verilog syntax and double checked the begin-end pairs but there's been no luck yet.
However, I have managed to get some values across the channel and received by the ADC. I guess my assumption about the reference design input being twos complement was incorrect.
There is some strange behaviour with the transmitted signal. As you can see, the values being input to the DAC (shown on the dac_dbg_data pins from the design, dark red in and dark blue quad) are square waves with the in-phase and quadrature phase offset by 1/4 the period. However, a strange discontinuity effect is seen by the signals received by the ADC (light red in and light blue quad). These signals are attached to "dac_dds_data_x" within axi_ad9122_channel.v only.
The effect also ocurrs when the signals are shifted by 1/8 the period (in blue and quad green):
Do you have any ideas as to what may be causing this behaviour?
Thanks,
Stephen