Thank you, Prashant. The EZ-KIT schematic has a nearly identical solution to what I came up with. The only difference in the logic is that I reduced A20 = AND(AMS0, AMS1), whereas the solution in the EZ-KIT has A20 = NAND(AMS2, AMS3). Logically, they are equivalent if I made correct assumptions about "don't care" states.
When no ASYNC address lines are active, A[21:20] will default to '11' in my implementation rather than '01' in the EZ-KIT. This shouldn't matter since CSn is never active low during such a transition. Another benefit to my solution is that I can use a quad-package 2-input AND chip (SN74ALVC08) and save board space.
Am I correct in assuming that no two AMSx lines will be simultaneously active low during an asynchronous read/write?
-Jason
