Ian,
Which xco file are you referring to?
This question has been asked many times before. At present all of our reference designs are Verilog with a few exceptions. Unless it is a behavioral code, you shouldn't have any problems relating verilog and VHDL code each other. I don't know of any tools that cares about it either - only people. It used to be that you need a wrapper and that sort - but all seamless now. What I am saying is that - you can still develop your algorithms in VHDL and instantiate them in the design. If you ran into problems let us know- we will be glad to help.
Thanks,
Rejeesh