What is the timing of DRDY with respect to MClk? I am using an FPGA and want to use synchronous logic so need to latch DRDY with MClk (= IClk) or do I have to latch DRDY in a set/reset latch because DRDY is not guaranteed to be valid at either MCLk rising or falling edge?
Next timing question: how many IClks after Sync does the first DRDY occur? Has anyone got a version of Table 6 from tha data sheet that is in units of IClk, not uS? Many thanks Dave