Zedboard ADV7511 HDL reference design - Vivado

Analog Devices provided the reference HDL design for ADV7511 for zedboard for Vivado.

I downloaded the designs from
http://wiki.analog.com/resources/fpga/docs/hdl#building_on_vivado

Then, when I built the libraries and source the tcl files,

I got errros in Vivado 2014.3

Error is:

[IP_Flow 19-3461] Value 'IIC_MAIN' is out of the range for parameter 'IIC Board Interface(IIC_BOARD_INTERFACE)' for BD Cell '/axi_iic_main' . Valid values are - Custom