Matt,
Please see the original thread - it has the script file attached; in the order implemented. As I explained in the original thread, while inputting 1080i60 on a 10-bit multiplexed 422 DDR clocked bus (bus clk = pixel clk, not 2 xpclk) and mapped to the ADV7513 D9:D0 input pins, I do get an output image but only when register 0x15 is incorrectly set for SDR bus (=0x04). Under this condition, the monitor reports that the received format is 952x540 resolution, not 1920x1080. And under this condition I get an image. I have the ability to invert the DDR input clock phase and with one phase I get incorrect color but a good image, under the other phase I get the same image with very muted colors and lots of noise running through the image.
When I change register 0x15=0x08 (DDR bus setting for ID=8, Style 2), I get nothing, the monitors will not recognize the video. Under either setting for register 0x15, the PLL lock register reports a lock and no other error.
I have also tried CSC enabled and attempted outputting RGB444 but without any success.
If it would help, I can send photos of the monitor outputs. Please let me know.
Regards,
Guy