Many thanks Craig and Joe for your suggestions.
Yes, I am maintaining VDDEXT during hibernation. It's only the 3.3 V (powers the SDRAM, FLASH and peripherals) which is switched off during hibernation. I use the presence of the VDDINT to switch the 3.3V so the cold start power up process is...
VDDEXT(ON) -> VDDINT(ON) -> 3.3V(ON). During hibernation VDDINT goes down which then switches off the 3.3V supply so its..
VDDIN(OFF) -> 3.3V (OFF) . The problem was that the processor would not (re)boot correctly after hibernation.
After waking from hibernation the Blackfin initiates a software reset which checks the state of BMODE and then (assuming its set for FLASH access), tries to load from the EEPROM. The first read from the FLASH happens about 200 us after the reset. Unfortunately, the 3.3V power supply regulator (ADP2302) has a soft start function which ramps up the 3.3V over a period of 2048 cycles of the switching frequency (700 kHz) which equates to about 3 ms. So, the problem is that the FLASH is not powered when the Blackfin is attempting its first read access. The processor boots correctly on cold start because it has a reset circuit which holds off SDRAM access until the 3.3 V has stabilised. There's no hardware reset after hibernation which means the processor tries to access the FLASH within the 200 us period and consequently hangs.
Fortunately, I found a neat way round the problem which might be useful for other designers. The solution is to use the BR pin on the Blackfin. BR will hold off accesses to memory until BR goes high. A simple reset RC addition (33k and 200 nF) to the BR pin using the 3.3V switched rail will provide a delay of 6.6 ms and hold off access until the 3.3V supply is stable. I haven't tried it but the PGOOD from the ADP2302 device in the 3.3V supply could also be used to hold off the processor accesses via BR.
My circuit is now running with a hibernate current of less than 1 mA and I can use conventional SDRAM instead of mSDRAM without all of the consequent complications of the mSDRAM 1.8 V rails. (Note that the self refresh of SDRAM would still maintain a quiescent current of around 8 mA unless its shut down completely by removing its supply rails, as done here). I use the standard EZ-KIT configuration and don't need any additional components to handle the hibernate function. SDRAM memory contents aren't retained during the hibernate but I simply load critical parameters into an empty block in the FLASH prior to hibernation and then recover them after the software reset.
Thanks again for your help and hope this is useful for someone else.
Cheers
Ian