Dave,
Point taken on using the CLKOUT to drive my clock buffer. I have used the XTALOUT before in other designs and may have gotten away with it in a less critical situation. I was afraid If I used the buffered CLKOUT it would impart a minor delay that I didn't want to risk. But sounds like it would be well under the clock's window to lock onto.
If I understand you correctly, you would advise NOT having two ADC masters, one for each TDM8 stream? Does this have to do with the ADCs' PLLs not being synchronized more so than having the same MCLK source? Is there a way to remedy this, as I would prefer this scenario given that my layout has 2 ADCs on each side of the dsp. And how essential is it that that all 16 channels be sampled during the same LRCLK period? Coming into the dsp on 2 separate TDM8 bitstreams, won't the separate clock domains from each ADC (and the one going to the DAC) take care of that, as if they originated from two separate, unsynchronized clock sources? Or am I begging the question of possibly having to use the onboard ASRCs?
I suppose I could provide jumpers on my proto board to reconfigure and evaluate each scenario before committing.
If it matters, I also have 2 WM8804 spdif transceivers in the design (not using 1452's onboard spdif) which provide I2S outputs which will feed SDAT _IN2&3, and go out on SDATA_OUT2&3. These too will get their MCLK from the clock buffer and will have their BCLK/LRCLK driving the dsp's remaining clock domains 2&3.
Speaking of the DAC, would the two SDAT_OUT lines from the dsp have to be assigned to their own clock domains, namely BCLKOUT0/LRCLKOUT0 and BCLKOUT1/LRCLKOUT1 respectively, or can I assign them both to clock domain 0, as I could on the ADAU1446?
IF the first case, is it OK to tie the 2 clock domains together, i.e, "Y" the DAC clocks into both?
Really appreciate the speedy and thorough reply to my first post. This is all really helpful.
thanks,
chuck
