Hello Philipp,
The 1761's versatile PLL allows using a MCLK range from 8 to 27 MHz while maintaining a core clock of approx. 45 to 49 MHz. When the PLL is in use, the core clock is always 1024 times the base sample rate -- 45.158 MHz for 44.1 KHz, or 49.152 MHz for 48 KHz. To get multiples of the nominal 44.1 K or 48 K sample rates, set the separate DSP and converter sampling rate registers. To avoid aliasing, these should be set identically.
For example, when I set the DSP sample rate to 8 KHz (nominal sample rate / 6), but leave the converters at nominal, I hear awful aliasing -- as you noted, this is because the converters' digital filters are running at an inappropriate frequency. To eliminate the aliasing, I also need to set the converters to the same frequency. With this done, we get "muffled", telephone quality audio -- but no aliasing.
The core clock can only deviate from the nominal frequencies within a limited range. For example, with the normal PLL setting for a 12.288 KHz, a 440 Hz oscillator in the project sounds exactly middle A. Changing the PLL to fractional mode, N = 1. M = 2, R = 4, makes the note a slightly sharp B. Attempting a core clock (PLL output) too far from nominal prevents the PLL from locking.
Best regards,
Bob