Hi Siva.
From ADE7878 datasheet timing diagram on page 12, you want a default SCLK that is high.
You can change MOSI on the falling edge of SCLK so that it has had enough setup time before it is sampled on the rising edge.
ADE7878 changes MISO on the falling edge of SCLK so you should wait until this data is valid to read it. Basically you want to read the MISO data on the rising edge of SCLK.
It's a bit hard to understand the code. An oscilloscope capture would be the best way to debug.
That said, it looks like you have two instructions which manipulate MOSI, MISO and SCLK for each bit that is sent.
I think you output MOSI and sample MISO on the rising edge of SCLK.
I think you need to change the default state of SCLK to be high and you want to change your input sampling to be on the next SCLK edge. So, swap the c<<=1; and ret<<=1 lines in your code.
Please review the SPI timing diagrams in the datasheet. If you would like further assistance with this, please provide oscilloscope waveforms of the communication.
Best Regards
Meghan