- I am generating the plots with ADIsimPLL. I have attached the simulation I am using. The simulation is also used to design the loop filter. You will need to download our free tool to open the simulation: www.analog.com/adisimpll (form is approved immediately). When you open the simulation, go to the Frequency Domain tab. Right click on the Phase Noise plot and click Scale > Axes to change the scale.
- The loop filter change requires changing 5 components - R1, R2, C1, C2, and C3. I designed a filter with a LBW of 112 kHz using ADIsimPLL. This is it:
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I soldered it onto a standard evaluation board (the same as the one you have) and then did a lock time measurement on an oscilloscope. I triggered off the rising-edge of LE and monitored the LD (Lock Detect) testpoint. I repeatedly wrote to R0 and watched the result on the oscilloscope. Of about 100 writes, all were between 27 - 35 µs.
In the attached image: green = LE; blue = Lock Detect.