Hi Istvan,
Thanks replying for my request,
We are using AD9364 in our design for custom data acquisition board, initially we planned to try the reference HDL provides from AD website and implement the same in xilinx - vivado for Zync SoC. But in altera by using mega function wizard we thought of generating these file and the same is shown above, but without altlvds_tx_rx files synthesis was possible in vivado, could you please suggest how to alter the code for 1 recieve and transmit channel including all attributes present in reference HDL, as we are using only single channel in the AD9364 IC.
Regards
J K Ranjan
