GuenterL,
I have not used the scope yet, but the 65 MHz HDMI_clk provided to ADV7513 is the same clock source to generate video output, clk was generated by a PLL, goes out of the FPGA via a ODDR2 clock output buffer recommended by Xilinx.
- All HDMI data lines as well as HSYNC, VSYNC, DE were driven by XIlinx LVCMOS33 IO pads
- TMDS lines, HPD pin were connected directly from ADV7513 to the HDMI connector (with 5 V power) .
- The ADV7513 and HDMI connector are less than 1/4 inch apart physically on the board.
- CEC feature is not used, so I drive this CEC_CLK low. The Audio signal group is not used, were left open.. is it harmful? (I did not design this board, got a job to make it work ... lol)
Please, see the portion of schematic attached.
Perhaps, next step is using the oscilloscope .... or any hint(s) you could think of ?
I've been stuck with this for a month now, first the translation of 7-bit slave address, now the darkness on the monitor.
Thank you for spending time to help me out, very appreciated.
K
