Hi Vijay,
1. You are correct. When you use Flash based configuration, the IAR downloads the code in internal SPI Flash memory of processor and applies a reset. So, while debugging, you can use SRAM based configuration
2. Can you provide more details about your observation: event data register shows some wrong value. What values you see at 1.7V, 1.0V and 0.0V?
Are you giving analog input to pin-9 of Analog connector J9? If yes, are you given channel ID as 4 in the ADC control word (if you are referering EE-365 codes, then CHNL_ID macro as 4)?
And whether you are using internal reference or external reference for ADC? if external, are you installing JP1 & JP2 jumpers?
-Prashant