I programmed the FPGA with the cf_fmc176_zc706.bit file using iMPACT. However, no characters are displaying on the UART terminal. Also, Chipscope finds 3 ILA cores, but when I trigger each of them on wildcard bits (i.e., trigger = xx), I get the message "Waiting for core to be armed, slow or stopped clock" for all 3 ILAs.
I read the JESD204B Xilinx/Analog Devices AD9250 Interoperability Report where it states "An external Device Clock/GT Reference clock is connected to the FMC card, this clock is forwarded via the FMC interface to a GT reference clock input of the FPGA." Do I need to supply the AD-FMCJESDADC1-EBZ with a clock for the reference design to work? Does this explain the Chipscope message?
Message was edited by: Rohan Ramlall