Hi schichen717,
I noticed that vias are used for the MCLK connections which also add up to the total load capacitance. As mentioned, this will make the lines imbalance. So, it is best to make these traces identical and running on the same layer as much as possible. Treating MCLK lines as important lines in the PCB (same length, same width, short as possible, etc) should be considered in early stage of PCB design.
The 1-MegOhm resistor between the MCLK acts as a filter with the combination of the load capacitance. If this resistor is removed, the source impedance will take its place which depends of its value. Therefore, the external clock must provide a balanced load going to the MCLK pins.
Regards,
Johnny