OK, well now this is getting more interesting!
Let me try to break down the problem here. I find it easier to collect my thoughts by writing them down...
DSP1 has two input clock domains - DIX9211 and DSP2.
DSP1 has two output clock domains - DSP2 and DIT4192.
Let's start with DSP1.
It would be easiest if DSP1's outputs could be masters. This would mean that DSP2 and DIT4192 would be slaves to DSP1. Therefore, on the input side of DSP1, only one set of ASRCs is needed to handle the asynchronous input from DIX9211.
SDATA_IN0, SDATA_IN1, and SDATA_IN2, will be slaves to the clocks coming in on BCLK0/LRCLK0, BCLKIN1/LRCLK1, and BCLK2/LRCLK2. The data from SDATA_IN0 goes to ASRC0. The data from SDATA_IN1 goes to ASRC1. The data from SDATA_IN2 goes to ASRC2.
SDATA_IN3 (BCLK3/LRCLK3), SDATA_IN4 (BCLK4/LRCLK4), and SDATA_IN5 (BCLK5/LRCLK5) will be set up as masters. Their clock pins will be routed to the corresponding pins (BCLK6/LRCLK6, BCLK7/LRCLK7, BCLK8/LRCLK8) on DSP2.
SDATA_OUT6 (BCLK6/LRCLK6), SDATA_OUT7 (BCLK7/LRCLK7), and SDATA_OUT8 (BCLK8/LRCLK8) will be set up as masters. Their clock pins will be routed to the corresponding pins on DSP2 (BCLK3/LRCLK3, BCLK4/LRCLK4, BCLK5/LRCLK5).
SDATA_OUT0 (BCLK9/LRCLK9), SDATA_OUT1 (BCLK10/LRCLK10), and SDATA_OUT2 (BCLK11/LRCLK11) will be set up as masters. Their clocks will be routed to the DIT4192.
OK, now on to DSP2.
SDATA_IN0, SDATA_IN1, and SDATA_IN2, will be slaves to the clocks coming in on BCLK0/LRCLK0, BCLKIN1/LRCLK1, and BCLK2/LRCLK2. The data from SDATA_IN0 goes to ASRC0. The data from SDATA_IN1 goes to ASRC1. The data from SDATA_IN2 goes to ASRC2.
SDATA_IN3 (BCLK3/LRCLK3), SDATA_IN4 (BCLK4/LRCLK4), and SDATA_IN5 (BCLK5/LRCLK5) will be set up as slaves to DSP1.
SDATA_OUT6 (BCLK6/LRCLK6), SDATA_OUT7 (BCLK7/LRCLK7), and SDATA_OUT8 (BCLK8/LRCLK8) will be set up as slaves to DSP1.
SDATA_OUT0 (BCLK9/LRCLK9), SDATA_OUT1 (BCLK10/LRCLK10), and SDATA_OUT2 (BCLK11/LRCLK11) will be set up as slaves to DSP1. You'll need to route the appropriate clock signals to those pins. These clocks are copies of the clocks being routed to the DIT4192.
Now, it's important that DSP1 is set to have its DSP Start Pulse internal (since it is the master) and to have DSP2 set its DSP Start Pulse to come from a serial port that is a slave to DSP1. This will put the two DSP cores in sync, I think.
So, with those recommendations, I think you're all set.