Hi lunke029,
I just used my evaluation board and tried a simple test. I routed data output from SDATA_OUT0 in master mode, using clocks LRCLK9/BCLK9.
I connected these signals using jumper wires to SDATA_IN5, LRCLK5, and BCLK5, respectively. Serial input port is set as a slave, and it is a slave to clock domain 5.
I also configured clock domain 5 to assign it to the input ports.
Then I created a simple test project that generates a sine tone inside the DSP core and sends it to SDATA_OUT0, and it takes the input from SDATA_IN5 and feeds it to level detectors.
When I compile the project, I don't experience any errors. The code downloads from the USBi and the device runs. I can see the 1 kHz sine tone appearing in the level detectors.
So, unfortunately, I'm not able to duplicate the problem you're seeing. The project file is attached for reference.