While it is good that using the HRM example solved the problem, the power services should also work for that processor. I would expect the PLL_DIV register to update to 0x4 as a result of your original use of the service. Since you seem to have proven that it comes back as 15, I'd be interested in understanding why. How do you then set the PLL_DIV register after that? You said you set it to 0x4 yourself and that you can read that the register is indeed 4, but you still observe an SCLK of 26.6 MHz...how are you doing this? Writes to the PLL_DIV register do not require any kind of PLL programming sequence and can occur dynamically. If you are writing 0x4 to the PLL_DIV register, there is no way your SCLK should still be 26.6 MHz unless the core clock is also being changed back to ~100 MHz at the same time...which is why I am asking for the procedure you use.
-Joe