Hi Dragos,
I tried to use dac_dma_setup() instead of dds_setup(), with DAC sampling frequency set to 61.44MSPS.
It seems that -although everything was looking good for DDS case- the output of DAC (using the dac_dma_setup) is again appearing at fs = 61.44M/2 = 30.72MSPS.
2 facts are showing this:
1) output spectrum shows periodicity at 30.72MHz:
2) output signal frequency is 960kHz = 30.72M / 32. (32 is the number of samples/cycle in the LUT -I checked it too and it will change correspondingly if you change the samples/cycle of LUT- ).
checking out the time samples also admits the fs = 30.72MHz.
My problem is that I've set the dac-fs to 61.44M not to 30.72M and I'm getting 30.72M out. Basically I've no problem if the sampling rate is -really- 30.72, but problem arises when for example I want to apply x2 or higher interpolations in the DAC: then registers show that fs = 61.44M which is inconsistent, and it will cause a problem.
you can find my modified code I used (mainly: test.c and main.c + some other modified files) as attachments.
Could you please check to see if we can run the DDR samples with fully controlled desirable 61.44M sample rate?
Bests,
FArid