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Re: Glitch from ADG1412 spice model switch

April 10, 2018, 11:04 pm
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Hi Antoine,

 

I'm looking into this. I'll get back to you in a short while.

 

Best Regards,

May

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Search

Where can I find the instruction of the reference design?

April 10, 2018, 11:09 pm
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I am trying to use the AD-FMCJESDADC1-EBZ with a ZC706 board. And I have made a FPGA project sucessfully with the reference design. But I didn't find enough instruction of the reference design. Where does the output data  go after it 

is transfered in the FPGA? How can I observe the output data through the UART terminal?

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Can a single TCXO be used as reference for 4 PLL ADF5355?

April 10, 2018, 11:11 pm
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Hi, i want to synchronize 4 ADF5355 chips with single TX-503 oscillator. What considerations should i be taking ?

 

Faiz

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ADV7181C 480i YPrPb In 12Bit RGB DDR, setting?

April 10, 2018, 11:15 pm
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hi, i using the adv7181C my own board.

 

My system needs to receive various inputs.(1080i , 720p , 480i, 480p)

The 1080i and 720p inputs are currently working well.

Currently my system detects the input to STDI and changes the PRIM_MODE and VID_STD registers.

(1080i : PRIM_MODE = 0x01, VID_STD  = 0x0c, 720p : PRIM_MODE = 0x01, VID_STD  = 0x0a)

 

BUT, when input is  480i or 480p,  do not work.

 

 

if i want 480i/p YprPb in, 12bit RGB DDR out, 

What registers should I change?



 

And https://ez.analog.com/thread/37874 

In this document, someone answered that PRIM_MODE and VID_STD are for free run mode, is this true?

 

 

 

thank you.

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Re: The AD9364 output spurious signal is too large

April 11, 2018, 12:32 am
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Hi  srimoyi，

Thank you very much for your reply！

Can you share the configuration parameters. Are you looping back TX to RX? If yes can you share the RX plot.

The following is a system block diagram of 9364.  Configuration parameters at the bottom.

What is the type of the signal that you are giving to the AD9364 input? Is it a CW tone or a modulated signal?

CW signal.

 

Can you check by giving standard LTE 5MHz signal to the input.

I don't have a standard 5MHz LTE signal. Filter parameters I was configured according to LTE 3MHz，Is there any problem with this?

Are you running all the initialization calibrations properly as mentioned in  page 6 of UG 570?

I am running all the initialization calibrations in  page 6 of UG-673

 

//************************************************************
// AD9361 R2 Auto Generated Initialization Script: This script was
// generated using the AD9361 Customer software Version 2.1.1


u8 AD9364_Init(void)
{
u16 count;
u8 temp_data;
AD9364_HW_Init();
//RESET_FPGA
//RESET_DUT
//BlockWrite 2,0x6 // Set ADI FPGA SPI to 20Mhz
AD9364_Write_Reg(0x3DF,0x01);
//ReadPartNumber
AD9364_Write_Reg(0x295,0x14); // Power up XO path (Default)
AD9364_Write_Reg(0x2A6,0x0E); // Enable Master Bias
AD9364_Write_Reg(0x2A8,0x0E); // Set Bandgap Trim
//REFCLK_Scale 40.000000,0x1,0x2 // Sets local variables in script engine,0x user can ignore
//AD9364_Write_Reg(0x292,0x08); // Set DCXO Coarse Tune[5:0]
//20180302
AD9364_Write_Reg(0x292,0x0d); // Set DCXO Coarse Tune[5:0]

AD9364_Write_Reg(0x293,0x80); // Set DCXO Fine Tune [12:5]
AD9364_Write_Reg(0x294,0x00); // Set DCXO Fine Tune [4:0]
AD9364_Write_Reg(0x2AB,0x07); // Set RF PLL reflclk scale to REFCLK * 2
AD9364_Write_Reg(0x2AC,0xFF); // Set RF PLL reflclk scale to REFCLK * 2
AD9364_Write_Reg(0x009,0x07); // Enable Clocks
//20180302
//AD9364_Write_Reg(0x00a,0x31); // Enable Clock out

//WAIT 20 // waits 20 ms
delay_ms(20); //waits 20 ms

//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************
AD9364_Write_Reg(0x045,0x00); // Set BBPLL reflclk scale to REFCLK /1
AD9364_Write_Reg(0x046,0x03); // Set BBPLL Loop Filter Charge Pump current
AD9364_Write_Reg(0x048,0xE8); // Set BBPLL Loop Filter C1,0x R1
AD9364_Write_Reg(0x049,0x5B); // Set BBPLL Loop Filter R2,0x C2,0x C1
AD9364_Write_Reg(0x04A,0x35); // Set BBPLL Loop Filter C3,0xR2
AD9364_Write_Reg(0x04B,0xE0); // Allow calibration to occur and set cal count to 1024 for max accuracy
AD9364_Write_Reg(0x04E,0x10); // Set calibration clock to REFCLK/4 for more accuracy
AD9364_Write_Reg(0x043,0x29); // BBPLL Freq Word (Fractional[7:0])
AD9364_Write_Reg(0x042,0x5C); // BBPLL Freq Word (Fractional[15:8])
AD9364_Write_Reg(0x041,0x12); // BBPLL Freq Word (Fractional[23:16])
AD9364_Write_Reg(0x044,0x18); // BBPLL Freq Word (Integer[7:0])
AD9364_Write_Reg(0x03F,0x05); // Start BBPLL Calibration
AD9364_Write_Reg(0x03F,0x01); // Clear BBPLL start calibration bit
AD9364_Write_Reg(0x04C,0x86); // Increase BBPLL KV and phase margin
AD9364_Write_Reg(0x04D,0x01); // Increase BBPLL KV and phase margin
AD9364_Write_Reg(0x04D,0x05); // Increase BBPLL KV and phase margin

//WAIT_CALDONE BBPLL,0x2000 // Wait for BBPLL to lock,0x Timeout 2sec,0x Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)
//SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked)

for(count=0;count<2000;count++) // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x05E);
if((temp_data&0x80)==0x80)
break;
}
if(count>=2000)
return 0;

AD9364_Write_Reg(0x002,0xDE); // Setup Tx Digital Filters/ Channels
AD9364_Write_Reg(0x003,0xDE); // Setup Rx Digital Filters/ Channels
AD9364_Write_Reg(0x004,0x03); // Select Rx input pin(A,0xB,0xC)/ Tx out pin (A,0xB)
//AD9364_Write_Reg(0x004,0x30); // Select Rx input pin(A,0xB,0xC)/ Tx out pin (A,0xB)


//AD9364_Write_Reg(0x00A,0x04); // Set BBPLL post divide rate
//20180302
AD9364_Write_Reg(0x00A,0x14); // Set BBPLL post divide rate

//************************************************************
// Program Tx FIR: D:\Program Files\Analog Devices\AD9361R2
// Evaluation Software\DigitalFilters\LTE3_MHz.ftr
//************************************************************
AD9364_Write_Reg(0x065,0xFA); // Enable clock to Tx FIR Filter and set Filter gain Setting
//WAIT 1 // waits 1 ms
delay_ms(1);
AD9364_Write_Reg(0x060,0x00); // Write FIR coefficient address
AD9364_Write_Reg(0x061,0xFE); // Write FIR coefficient data[7:0]
AD9364_Write_Reg(0x062,0xFF); // Write FIR coefficient data[15:8]
AD9364_Write_Reg(0x065,0xFE); // Set Write EN to push data into FIR filter register map
AD9364_Write_Reg(0x064,0x00); // Write to Read only register to delay ~1us
AD9364_Write_Reg(0x064,0x00); // Write to Read only register to delay ~1us
AD9364_Write_Reg(0x060,0x01);
AD9364_Write_Reg(0x061,0xFE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x02);
AD9364_Write_Reg(0x061,0x01);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x03);
AD9364_Write_Reg(0x061,0x09);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x04);
AD9364_Write_Reg(0x061,0x0E);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x05);
AD9364_Write_Reg(0x061,0x0A);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x06);
AD9364_Write_Reg(0x061,0xFC);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x07);
AD9364_Write_Reg(0x061,0xF1);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x08);
AD9364_Write_Reg(0x061,0xFA);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x09);
AD9364_Write_Reg(0x061,0x0F);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x0A);
AD9364_Write_Reg(0x061,0x16);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x0B);
AD9364_Write_Reg(0x061,0x01);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x0C);
AD9364_Write_Reg(0x061,0xE3);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x0D);
AD9364_Write_Reg(0x061,0xE5);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x0E);
AD9364_Write_Reg(0x061,0x0F);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x0F);
AD9364_Write_Reg(0x061,0x31);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x10);
AD9364_Write_Reg(0x061,0x17);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x11);
AD9364_Write_Reg(0x061,0xD5);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x12);
AD9364_Write_Reg(0x061,0xBE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x13);
AD9364_Write_Reg(0x061,0xFF);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x14);
AD9364_Write_Reg(0x061,0x52);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x15);
AD9364_Write_Reg(0x061,0x46);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x16);
AD9364_Write_Reg(0x061,0xD3);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x17);
AD9364_Write_Reg(0x061,0x84);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x18);
AD9364_Write_Reg(0x061,0xD1);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x19);
AD9364_Write_Reg(0x061,0x73);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x1A);
AD9364_Write_Reg(0x061,0x97);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x1B);
AD9364_Write_Reg(0x061,0xEE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x1C);
AD9364_Write_Reg(0x061,0x3A);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x1D);
AD9364_Write_Reg(0x061,0x75);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x1E);
AD9364_Write_Reg(0x061,0x80);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x1F);
AD9364_Write_Reg(0x061,0x0E);
AD9364_Write_Reg(0x062,0x01);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x20);
AD9364_Write_Reg(0x061,0x3D);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x21);
AD9364_Write_Reg(0x061,0xED);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x22);
AD9364_Write_Reg(0x061,0xDD);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x23);
AD9364_Write_Reg(0x061,0x61);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x24);
AD9364_Write_Reg(0x061,0xA7);
AD9364_Write_Reg(0x062,0x01);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x25);
AD9364_Write_Reg(0x061,0xDB);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x26);
AD9364_Write_Reg(0x061,0xB7);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x27);
AD9364_Write_Reg(0x061,0xF9);
AD9364_Write_Reg(0x062,0xFD);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x28);
AD9364_Write_Reg(0x061,0xED);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x29);
AD9364_Write_Reg(0x061,0x57);
AD9364_Write_Reg(0x062,0x02);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x2A);
AD9364_Write_Reg(0x061,0xEC);
AD9364_Write_Reg(0x062,0x01);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x2B);
AD9364_Write_Reg(0x061,0xBE);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x2C);
AD9364_Write_Reg(0x061,0xBC);
AD9364_Write_Reg(0x062,0xFC);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x2D);
AD9364_Write_Reg(0x061,0xEE);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x2E);
AD9364_Write_Reg(0x061,0x09);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x2F);
AD9364_Write_Reg(0x061,0xA9);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x30);
AD9364_Write_Reg(0x061,0x42);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x31);
AD9364_Write_Reg(0x061,0x07);
AD9364_Write_Reg(0x062,0xFB);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x32);
AD9364_Write_Reg(0x061,0xF6);
AD9364_Write_Reg(0x062,0xFC);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x33);
AD9364_Write_Reg(0x061,0x9D);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x34);
AD9364_Write_Reg(0x061,0x99);
AD9364_Write_Reg(0x062,0x06);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x35);
AD9364_Write_Reg(0x061,0xD5);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x36);
AD9364_Write_Reg(0x061,0x6C);
AD9364_Write_Reg(0x062,0xF8);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x37);
AD9364_Write_Reg(0x061,0xC4);
AD9364_Write_Reg(0x062,0xF8);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x38);
AD9364_Write_Reg(0x061,0xDA);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x39);
AD9364_Write_Reg(0x061,0xDC);
AD9364_Write_Reg(0x062,0x0C);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x3A);
AD9364_Write_Reg(0x061,0xAE);
AD9364_Write_Reg(0x062,0x05);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x3B);
AD9364_Write_Reg(0x061,0x51);
AD9364_Write_Reg(0x062,0xF2);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x3C);
AD9364_Write_Reg(0x061,0x79);
AD9364_Write_Reg(0x062,0xEA);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x3D);
AD9364_Write_Reg(0x061,0x03);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x3E);
AD9364_Write_Reg(0x061,0xE2);
AD9364_Write_Reg(0x062,0x34);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x3F);
AD9364_Write_Reg(0x061,0xD9);
AD9364_Write_Reg(0x062,0x5D);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x40);
AD9364_Write_Reg(0x061,0xD9);
AD9364_Write_Reg(0x062,0x5D);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x41);
AD9364_Write_Reg(0x061,0xE2);
AD9364_Write_Reg(0x062,0x34);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x42);
AD9364_Write_Reg(0x061,0x03);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x43);
AD9364_Write_Reg(0x061,0x79);
AD9364_Write_Reg(0x062,0xEA);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x44);
AD9364_Write_Reg(0x061,0x51);
AD9364_Write_Reg(0x062,0xF2);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x45);
AD9364_Write_Reg(0x061,0xAE);
AD9364_Write_Reg(0x062,0x05);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x46);
AD9364_Write_Reg(0x061,0xDC);
AD9364_Write_Reg(0x062,0x0C);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x47);
AD9364_Write_Reg(0x061,0xDA);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x48);
AD9364_Write_Reg(0x061,0xC4);
AD9364_Write_Reg(0x062,0xF8);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x49);
AD9364_Write_Reg(0x061,0x6C);
AD9364_Write_Reg(0x062,0xF8);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x4A);
AD9364_Write_Reg(0x061,0xD5);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x4B);
AD9364_Write_Reg(0x061,0x99);
AD9364_Write_Reg(0x062,0x06);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x4C);
AD9364_Write_Reg(0x061,0x9D);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x4D);
AD9364_Write_Reg(0x061,0xF6);
AD9364_Write_Reg(0x062,0xFC);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x4E);
AD9364_Write_Reg(0x061,0x07);
AD9364_Write_Reg(0x062,0xFB);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x4F);
AD9364_Write_Reg(0x061,0x42);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x50);
AD9364_Write_Reg(0x061,0xA9);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x51);
AD9364_Write_Reg(0x061,0x09);
AD9364_Write_Reg(0x062,0x03);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x52);
AD9364_Write_Reg(0x061,0xEE);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x53);
AD9364_Write_Reg(0x061,0xBC);
AD9364_Write_Reg(0x062,0xFC);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x54);
AD9364_Write_Reg(0x061,0xBE);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x55);
AD9364_Write_Reg(0x061,0xEC);
AD9364_Write_Reg(0x062,0x01);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x56);
AD9364_Write_Reg(0x061,0x57);
AD9364_Write_Reg(0x062,0x02);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x57);
AD9364_Write_Reg(0x061,0xED);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x58);
AD9364_Write_Reg(0x061,0xF9);
AD9364_Write_Reg(0x062,0xFD);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x59);
AD9364_Write_Reg(0x061,0xB7);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x5A);
AD9364_Write_Reg(0x061,0xDB);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x5B);
AD9364_Write_Reg(0x061,0xA7);
AD9364_Write_Reg(0x062,0x01);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x5C);
AD9364_Write_Reg(0x061,0x61);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x5D);
AD9364_Write_Reg(0x061,0xDD);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x5E);
AD9364_Write_Reg(0x061,0xED);
AD9364_Write_Reg(0x062,0xFE);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x5F);
AD9364_Write_Reg(0x061,0x3D);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x60);
AD9364_Write_Reg(0x061,0x0E);
AD9364_Write_Reg(0x062,0x01);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x61);
AD9364_Write_Reg(0x061,0x80);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x62);
AD9364_Write_Reg(0x061,0x75);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x63);
AD9364_Write_Reg(0x061,0x3A);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x64);
AD9364_Write_Reg(0x061,0xEE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x65);
AD9364_Write_Reg(0x061,0x97);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x66);
AD9364_Write_Reg(0x061,0x73);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x67);
AD9364_Write_Reg(0x061,0xD1);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x68);
AD9364_Write_Reg(0x061,0x84);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x69);
AD9364_Write_Reg(0x061,0xD3);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x6A);
AD9364_Write_Reg(0x061,0x46);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x6B);
AD9364_Write_Reg(0x061,0x52);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x6C);
AD9364_Write_Reg(0x061,0xFF);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x6D);
AD9364_Write_Reg(0x061,0xBE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x6E);
AD9364_Write_Reg(0x061,0xD5);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x6F);
AD9364_Write_Reg(0x061,0x17);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x70);
AD9364_Write_Reg(0x061,0x31);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x71);
AD9364_Write_Reg(0x061,0x0F);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x72);
AD9364_Write_Reg(0x061,0xE5);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x73);
AD9364_Write_Reg(0x061,0xE3);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x74);
AD9364_Write_Reg(0x061,0x01);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x75);
AD9364_Write_Reg(0x061,0x16);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x76);
AD9364_Write_Reg(0x061,0x0F);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x77);
AD9364_Write_Reg(0x061,0xFA);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x78);
AD9364_Write_Reg(0x061,0xF1);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x79);
AD9364_Write_Reg(0x061,0xFC);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x7A);
AD9364_Write_Reg(0x061,0x0A);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x7B);
AD9364_Write_Reg(0x061,0x0E);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x7C);
AD9364_Write_Reg(0x061,0x09);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x7D);
AD9364_Write_Reg(0x061,0x01);
AD9364_Write_Reg(0x062,0x00);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x7E);
AD9364_Write_Reg(0x061,0xFE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x060,0x7F);
AD9364_Write_Reg(0x061,0xFE);
AD9364_Write_Reg(0x062,0xFF);
AD9364_Write_Reg(0x065,0xFE);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x064,0x00);
AD9364_Write_Reg(0x065,0xF8); // Disable clock to Tx Filter


//************************************************************
// Program Rx FIR: D:\Program Files\Analog Devices\AD9361R2
// Evaluation Software\DigitalFilters\LTE3_MHz.ftr
//************************************************************
AD9364_Write_Reg(0x0F5,0xFA); // Enable clock to Rx FIR Filter
AD9364_Write_Reg(0x0F6,0x02); // Write Filter Gain setting
//WAIT 1 // waits 1 ms
delay_ms(1);

AD9364_Write_Reg(0x0F0,0x00); // Write FIR coefficient address
AD9364_Write_Reg(0x0F1,0xFE); // Write FIR coefficient data[7:0]
AD9364_Write_Reg(0x0F2,0xFF); // Write FIR coefficient data[15:8]
AD9364_Write_Reg(0x0F5,0xFE); // Set Write EN to push data into FIR filter register map
AD9364_Write_Reg(0x0F4,0x00); // Dummy Write to Read only register to delay ~1us
AD9364_Write_Reg(0x0F4,0x00); // Dummy Write to Read only register to delay ~1us
AD9364_Write_Reg(0x0F0,0x01);
AD9364_Write_Reg(0x0F1,0xF9);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x02);
AD9364_Write_Reg(0x0F1,0xF8);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x03);
AD9364_Write_Reg(0x0F1,0xFC);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x04);
AD9364_Write_Reg(0x0F1,0x07);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x05);
AD9364_Write_Reg(0x0F1,0x0A);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x06);
AD9364_Write_Reg(0x0F1,0x01);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x07);
AD9364_Write_Reg(0x0F1,0xF1);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x08);
AD9364_Write_Reg(0x0F1,0xF2);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x09);
AD9364_Write_Reg(0x0F1,0x08);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x0A);
AD9364_Write_Reg(0x0F1,0x1B);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x0B);
AD9364_Write_Reg(0x0F1,0x0D);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x0C);
AD9364_Write_Reg(0x0F1,0xE7);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x0D);
AD9364_Write_Reg(0x0F1,0xD9);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x0E);
AD9364_Write_Reg(0x0F1,0x00);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x0F);
AD9364_Write_Reg(0x0F1,0x32);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x10);
AD9364_Write_Reg(0x0F1,0x2B);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x11);
AD9364_Write_Reg(0x0F1,0xE3);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x12);
AD9364_Write_Reg(0x0F1,0xB1);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x13);
AD9364_Write_Reg(0x0F1,0xE3);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x14);
AD9364_Write_Reg(0x0F1,0x4D);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x15);
AD9364_Write_Reg(0x0F1,0x63);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x16);
AD9364_Write_Reg(0x0F1,0xF0);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x17);
AD9364_Write_Reg(0x0F1,0x77);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x18);
AD9364_Write_Reg(0x0F1,0xA6);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x19);
AD9364_Write_Reg(0x0F1,0x61);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x1A);
AD9364_Write_Reg(0x0F1,0xBC);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x1B);
AD9364_Write_Reg(0x0F1,0x1F);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x1C);
AD9364_Write_Reg(0x0F1,0x33);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x1D);
AD9364_Write_Reg(0x0F1,0x39);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x1E);
AD9364_Write_Reg(0x0F1,0x5A);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x1F);
AD9364_Write_Reg(0x0F1,0x38);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x20);
AD9364_Write_Reg(0x0F1,0x88);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x21);
AD9364_Write_Reg(0x0F1,0xF5);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x22);
AD9364_Write_Reg(0x0F1,0x8D);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x23);
AD9364_Write_Reg(0x0F1,0x1E);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x24);
AD9364_Write_Reg(0x0F1,0xD1);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x25);
AD9364_Write_Reg(0x0F1,0x46);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x26);
AD9364_Write_Reg(0x0F1,0xD5);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x27);
AD9364_Write_Reg(0x0F1,0x96);
AD9364_Write_Reg(0x0F2,0xFD);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x28);
AD9364_Write_Reg(0x0F1,0x84);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x29);
AD9364_Write_Reg(0x0F1,0x7B);
AD9364_Write_Reg(0x0F2,0x02);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x2A);
AD9364_Write_Reg(0x0F1,0x7E);
AD9364_Write_Reg(0x0F2,0x02);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x2B);
AD9364_Write_Reg(0x0F1,0xFF);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x2C);
AD9364_Write_Reg(0x0F1,0x45);
AD9364_Write_Reg(0x0F2,0xFC);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x2D);
AD9364_Write_Reg(0x0F1,0x4E);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x2E);
AD9364_Write_Reg(0x0F1,0x1D);
AD9364_Write_Reg(0x0F2,0x03);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x2F);
AD9364_Write_Reg(0x0F1,0x6F);
AD9364_Write_Reg(0x0F2,0x04);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x30);
AD9364_Write_Reg(0x0F1,0xBB);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x31);
AD9364_Write_Reg(0x0F1,0x7B);
AD9364_Write_Reg(0x0F2,0xFA);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x32);
AD9364_Write_Reg(0x0F1,0x02);
AD9364_Write_Reg(0x0F2,0xFC);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x33);
AD9364_Write_Reg(0x0F1,0x8D);
AD9364_Write_Reg(0x0F2,0x03);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x34);
AD9364_Write_Reg(0x0F1,0xAC);
AD9364_Write_Reg(0x0F2,0x07);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x35);
AD9364_Write_Reg(0x0F1,0xB8);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x36);
AD9364_Write_Reg(0x0F1,0xD1);
AD9364_Write_Reg(0x0F2,0xF7);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x37);
AD9364_Write_Reg(0x0F1,0x36);
AD9364_Write_Reg(0x0F2,0xF7);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x38);
AD9364_Write_Reg(0x0F1,0x5C);
AD9364_Write_Reg(0x0F2,0x03);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x39);
AD9364_Write_Reg(0x0F1,0x66);
AD9364_Write_Reg(0x0F2,0x0E);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x3A);
AD9364_Write_Reg(0x0F1,0x9B);
AD9364_Write_Reg(0x0F2,0x07);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x3B);
AD9364_Write_Reg(0x0F1,0xFB);
AD9364_Write_Reg(0x0F2,0xF1);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x3C);
AD9364_Write_Reg(0x0F1,0x83);
AD9364_Write_Reg(0x0F2,0xE7);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x3D);
AD9364_Write_Reg(0x0F1,0x53);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x3E);
AD9364_Write_Reg(0x0F1,0xCC);
AD9364_Write_Reg(0x0F2,0x35);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x3F);
AD9364_Write_Reg(0x0F1,0x5F);
AD9364_Write_Reg(0x0F2,0x62);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x40);
AD9364_Write_Reg(0x0F1,0x5F);
AD9364_Write_Reg(0x0F2,0x62);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x41);
AD9364_Write_Reg(0x0F1,0xCC);
AD9364_Write_Reg(0x0F2,0x35);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x42);
AD9364_Write_Reg(0x0F1,0x53);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x43);
AD9364_Write_Reg(0x0F1,0x83);
AD9364_Write_Reg(0x0F2,0xE7);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x44);
AD9364_Write_Reg(0x0F1,0xFB);
AD9364_Write_Reg(0x0F2,0xF1);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x45);
AD9364_Write_Reg(0x0F1,0x9B);
AD9364_Write_Reg(0x0F2,0x07);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x46);
AD9364_Write_Reg(0x0F1,0x66);
AD9364_Write_Reg(0x0F2,0x0E);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x47);
AD9364_Write_Reg(0x0F1,0x5C);
AD9364_Write_Reg(0x0F2,0x03);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x48);
AD9364_Write_Reg(0x0F1,0x36);
AD9364_Write_Reg(0x0F2,0xF7);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x49);
AD9364_Write_Reg(0x0F1,0xD1);
AD9364_Write_Reg(0x0F2,0xF7);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x4A);
AD9364_Write_Reg(0x0F1,0xB8);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x4B);
AD9364_Write_Reg(0x0F1,0xAC);
AD9364_Write_Reg(0x0F2,0x07);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x4C);
AD9364_Write_Reg(0x0F1,0x8D);
AD9364_Write_Reg(0x0F2,0x03);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x4D);
AD9364_Write_Reg(0x0F1,0x02);
AD9364_Write_Reg(0x0F2,0xFC);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x4E);
AD9364_Write_Reg(0x0F1,0x7B);
AD9364_Write_Reg(0x0F2,0xFA);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x4F);
AD9364_Write_Reg(0x0F1,0xBB);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x50);
AD9364_Write_Reg(0x0F1,0x6F);
AD9364_Write_Reg(0x0F2,0x04);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x51);
AD9364_Write_Reg(0x0F1,0x1D);
AD9364_Write_Reg(0x0F2,0x03);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x52);
AD9364_Write_Reg(0x0F1,0x4E);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x53);
AD9364_Write_Reg(0x0F1,0x45);
AD9364_Write_Reg(0x0F2,0xFC);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x54);
AD9364_Write_Reg(0x0F1,0xFF);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x55);
AD9364_Write_Reg(0x0F1,0x7E);
AD9364_Write_Reg(0x0F2,0x02);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x56);
AD9364_Write_Reg(0x0F1,0x7B);
AD9364_Write_Reg(0x0F2,0x02);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x57);
AD9364_Write_Reg(0x0F1,0x84);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x58);
AD9364_Write_Reg(0x0F1,0x96);
AD9364_Write_Reg(0x0F2,0xFD);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x59);
AD9364_Write_Reg(0x0F1,0xD5);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x5A);
AD9364_Write_Reg(0x0F1,0x46);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x5B);
AD9364_Write_Reg(0x0F1,0xD1);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x5C);
AD9364_Write_Reg(0x0F1,0x1E);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x5D);
AD9364_Write_Reg(0x0F1,0x8D);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x5E);
AD9364_Write_Reg(0x0F1,0xF5);
AD9364_Write_Reg(0x0F2,0xFE);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x5F);
AD9364_Write_Reg(0x0F1,0x88);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x60);
AD9364_Write_Reg(0x0F1,0x38);
AD9364_Write_Reg(0x0F2,0x01);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x61);
AD9364_Write_Reg(0x0F1,0x5A);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x62);
AD9364_Write_Reg(0x0F1,0x39);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x63);
AD9364_Write_Reg(0x0F1,0x33);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x64);
AD9364_Write_Reg(0x0F1,0x1F);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x65);
AD9364_Write_Reg(0x0F1,0xBC);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x66);
AD9364_Write_Reg(0x0F1,0x61);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x67);
AD9364_Write_Reg(0x0F1,0xA6);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x68);
AD9364_Write_Reg(0x0F1,0x77);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x69);
AD9364_Write_Reg(0x0F1,0xF0);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x6A);
AD9364_Write_Reg(0x0F1,0x63);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x6B);
AD9364_Write_Reg(0x0F1,0x4D);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x6C);
AD9364_Write_Reg(0x0F1,0xE3);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x6D);
AD9364_Write_Reg(0x0F1,0xB1);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x6E);
AD9364_Write_Reg(0x0F1,0xE3);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x6F);
AD9364_Write_Reg(0x0F1,0x2B);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x70);
AD9364_Write_Reg(0x0F1,0x32);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x71);
AD9364_Write_Reg(0x0F1,0x00);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x72);
AD9364_Write_Reg(0x0F1,0xD9);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x73);
AD9364_Write_Reg(0x0F1,0xE7);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x74);
AD9364_Write_Reg(0x0F1,0x0D);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x75);
AD9364_Write_Reg(0x0F1,0x1B);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x76);
AD9364_Write_Reg(0x0F1,0x08);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x77);
AD9364_Write_Reg(0x0F1,0xF2);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x78);
AD9364_Write_Reg(0x0F1,0xF1);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x79);
AD9364_Write_Reg(0x0F1,0x01);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x7A);
AD9364_Write_Reg(0x0F1,0x0A);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x7B);
AD9364_Write_Reg(0x0F1,0x07);
AD9364_Write_Reg(0x0F2,0x00);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x7C);
AD9364_Write_Reg(0x0F1,0xFC);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x7D);
AD9364_Write_Reg(0x0F1,0xF8);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x7E);
AD9364_Write_Reg(0x0F1,0xF9);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F0,0x7F);
AD9364_Write_Reg(0x0F1,0xFE);
AD9364_Write_Reg(0x0F2,0xFF);
AD9364_Write_Reg(0x0F5,0xFE);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F4,0x00);
AD9364_Write_Reg(0x0F5,0xF8); // Disable clock to Rx Filter

//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
AD9364_Write_Reg(0x010,0xC8); // PPORT Config 1
AD9364_Write_Reg(0x011,0x00); // PPORT Config 2
AD9364_Write_Reg(0x012,0x02); // PPORT Config 3
AD9364_Write_Reg(0x006,0x0F); // PPORT Rx Delay (adjusts Tco Dataclk->Data)
AD9364_Write_Reg(0x007,0x00); // PPORT TX Delay (adjusts setup/hold FBCLK->Data)

//************************************************************
// Setup AuxDAC
//************************************************************
AD9364_Write_Reg(0x018,0x00); // AuxDAC1 Word[9:2]
AD9364_Write_Reg(0x019,0x00); // AuxDAC2 Word[9:2]
AD9364_Write_Reg(0x01A,0x00); // AuxDAC1 Config and Word[1:0]
AD9364_Write_Reg(0x01B,0x00); // AuxDAC2 Config and Word[1:0]
AD9364_Write_Reg(0x023,0xFF); // AuxDAC Manaul/Auto Control
AD9364_Write_Reg(0x026,0x00); // AuxDAC Manual Select Bit/GPO Manual Select
AD9364_Write_Reg(0x030,0x00); // AuxDAC1 Rx Delay
AD9364_Write_Reg(0x031,0x00); // AuxDAC1 Tx Delay
AD9364_Write_Reg(0x032,0x00); // AuxDAC2 Rx Delay
AD9364_Write_Reg(0x033,0x00); // AuxDAC2 Tx Delay

//************************************************************
// Setup AuxADC
//************************************************************
AD9364_Write_Reg(0x00B,0x00); // Temp Sensor Setup (Offset)
AD9364_Write_Reg(0x00C,0x00); // Temp Sensor Setup (Temp Window)
AD9364_Write_Reg(0x00D,0x03); // Temp Sensor Setup (Periodic Measure)
AD9364_Write_Reg(0x00F,0x04); // Temp Sensor Setup (Decimation)
AD9364_Write_Reg(0x01C,0x10); // AuxADC Setup (Clock Div)
AD9364_Write_Reg(0x01D,0x01); // AuxADC Setup (Decimation/Enable)

//************************************************************
// Setup Control Outs
//************************************************************
AD9364_Write_Reg(0x035,0x00); // Ctrl Out index
AD9364_Write_Reg(0x036,0xFF); // Ctrl Out [7:0] output enable

//************************************************************
// Setup GPO
//************************************************************
AD9364_Write_Reg(0x03A,0x27); // Set number of REFCLK cycles for 1us delay timer
AD9364_Write_Reg(0x020,0x00); // GPO Auto Enable Setup in RX and TX
AD9364_Write_Reg(0x027,0x03); // GPO Manual and GPO auto value in ALERT
AD9364_Write_Reg(0x028,0x00); // GPO_0 RX Delay
AD9364_Write_Reg(0x029,0x00); // GPO_1 RX Delay
AD9364_Write_Reg(0x02A,0x00); // GPO_2 RX Delay
AD9364_Write_Reg(0x02B,0x00); // GPO_3 RX Delay
AD9364_Write_Reg(0x02C,0x00); // GPO_0 TX Delay
AD9364_Write_Reg(0x02D,0x00); // GPO_1 TX Delay
AD9364_Write_Reg(0x02E,0x00); // GPO_2 TX Delay
AD9364_Write_Reg(0x02F,0x00); // GPO_3 TX Delay

AD9364_Write_Reg(0x261,0x00); // Set Rx LO Power mode
AD9364_Write_Reg(0x2A1,0x00); // Set Tx LO Power mode
AD9364_Write_Reg(0x248,0x0B); // Enable Rx VCO LDO
AD9364_Write_Reg(0x288,0x0B); // Enable Tx VCO LDO
AD9364_Write_Reg(0x246,0x02); // Set VCO Power down TCF bits
AD9364_Write_Reg(0x286,0x02); // Set VCO Power down TCF bits
AD9364_Write_Reg(0x249,0x8E); // Set VCO cal length
AD9364_Write_Reg(0x289,0x8E); // Set VCO cal length
AD9364_Write_Reg(0x23B,0x80); // Enable Rx VCO cal
AD9364_Write_Reg(0x27B,0x80); // Enable Tx VCO cal
AD9364_Write_Reg(0x243,0x0D); // Set Rx prescaler bias
AD9364_Write_Reg(0x283,0x0D); // Set Tx prescaler bias
AD9364_Write_Reg(0x23D,0x00); // Clear Half VCO cal clock setting
AD9364_Write_Reg(0x27D,0x00); // Clear Half VCO cal clock setting

AD9364_Write_Reg(0x015,0x04); // Set Dual Synth mode bit
AD9364_Write_Reg(0x014,0x05); // Set Force ALERT State bit
AD9364_Write_Reg(0x013,0x01); // Set ENSM FDD mode
//WAIT 1 // waits 1 ms
delay_ms(1);

AD9364_Write_Reg(0x23D,0x04); // Start RX CP cal
//WAIT_CALDONE RXCP,0x100 // Wait for CP cal to complete,0x Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1)
for(count=0;count<1000;count++) // Wait for CP cal to complete, Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1)
{
delay_us(1);
temp_data=AD9364_Read_Reg(0x244);
if((temp_data&0x80)==0x80)
break;
}
if(count>=1000)
return 0;

AD9364_Write_Reg(0x27D,0x04); // Start TX CP cal
//WAIT_CALDONE TXCP,0x100 // Wait for CP cal to complete,0x Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1)
for(count=0;count<1000;count++) // Wait for CP cal to complete, Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1)
{
delay_us(1);
temp_data=AD9364_Read_Reg(0x284);
if((temp_data&0x80)==0x80)
break;
}
if(count>=1000)
return 0;


//************************************************************
// FDD RX/TX Synth Frequency: 800.000000,0x850.000000 MHz
//************************************************************
//************************************************************
// Setup Synthesizer
//************************************************************
AD9364_Write_Reg(0x23A,0x4A); // Set VCO Output level[3:0]
AD9364_Write_Reg(0x239,0xC3); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
AD9364_Write_Reg(0x242,0x1F); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
AD9364_Write_Reg(0x238,0x78); // Set VCO Cal Offset[3:0]
AD9364_Write_Reg(0x245,0x00); // Set VCO Cal Ref Tcf[2:0]
AD9364_Write_Reg(0x251,0x0C); // Set VCO Varactor Reference[3:0]
AD9364_Write_Reg(0x250,0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
AD9364_Write_Reg(0x23B,0x92); // Set Synth Loop Filter charge pump current (Icp)
AD9364_Write_Reg(0x23E,0xD4); // Set Synth Loop Filter C2 and C1
AD9364_Write_Reg(0x23F,0xDF); // Set Synth Loop Filter R1 and C3
AD9364_Write_Reg(0x240,0x09); // Set Synth Loop Filter R3

//************************************************************
// Setup Synthesizer
//************************************************************
AD9364_Write_Reg(0x27A,0x4A); // Set VCO Output level[3:0]
AD9364_Write_Reg(0x279,0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0]
AD9364_Write_Reg(0x282,0x17); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
AD9364_Write_Reg(0x278,0x78); // Set VCO Cal Offset[3:0]
AD9364_Write_Reg(0x285,0x00); // Set VCO Cal Ref Tcf[2:0]
AD9364_Write_Reg(0x291,0x0E); // Set VCO Varactor Reference[3:0]
AD9364_Write_Reg(0x290,0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
AD9364_Write_Reg(0x27B,0x98); // Set Synth Loop Filter charge pump current (Icp)
AD9364_Write_Reg(0x27E,0xD4); // Set Synth Loop Filter C2 and C1
AD9364_Write_Reg(0x27F,0xDF); // Set Synth Loop Filter R1 and C3
AD9364_Write_Reg(0x280,0x09); // Set Synth Loop Filter R3

//AD9364_Write_Reg(0x233,0xCB); // Write Rx Synth Fractional Freq Word[7:0]
//AD9364_Write_Reg(0x234,0xCC); // Write Rx Synth Fractional Freq Word[15:8]
//AD9364_Write_Reg(0x235,0x0C); // Write Rx Synth Fractional Freq Word[22:16]
//AD9364_Write_Reg(0x232,0x00); // Write Rx Synth Integer Freq Word[10:8]
//AD9364_Write_Reg(0x231,0x4B); // Write Rx Synth Integer Freq Word[7:0]
//AD9364_Write_Reg(0x005,0x32); // Set LO divider setting
//
//AD9364_Write_Reg(0x273,0x11); // Write Tx Synth Fractional Freq Word[7:0]
//AD9364_Write_Reg(0x274,0x5A); // Write Tx Synth Fractional Freq Word[15:8]
//AD9364_Write_Reg(0x275,0x64); // Write Tx Synth Fractional Freq Word[22:16]
//AD9364_Write_Reg(0x272,0x00); // Write Tx Synth Integer Freq Word[10:8]
//AD9364_Write_Reg(0x271,0x56); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
//AD9364_Write_Reg(0x005,0x32); // Set LO divider setting

//20180327 key
//AD9364_Write_Reg(0x233,0x11); // Write Rx Synth Fractional Freq Word[7:0]
//AD9364_Write_Reg(0x234,0x5A); // Write Rx Synth Fractional Freq Word[15:8]
//AD9364_Write_Reg(0x235,0x64); // Write Rx Synth Fractional Freq Word[22:16]
//AD9364_Write_Reg(0x232,0x00); // Write Rx Synth Integer Freq Word[10:8]
//AD9364_Write_Reg(0x231,0x56); // Write Rx Synth Integer Freq Word[7:0]
//AD9364_Write_Reg(0x005,0x23); // Set LO divider setting
//
//AD9364_Write_Reg(0x273,0xCB); // Write Tx Synth Fractional Freq Word[7:0]
//AD9364_Write_Reg(0x274,0xCC); // Write Tx Synth Fractional Freq Word[15:8]
//AD9364_Write_Reg(0x275,0x0C); // Write Tx Synth Fractional Freq Word[22:16]
//AD9364_Write_Reg(0x272,0x00); // Write Tx Synth Integer Freq Word[10:8]
//AD9364_Write_Reg(0x271,0x4B); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
//AD9364_Write_Reg(0x005,0x23); // Set LO divider setting

//20180402 car
//rx_c 751mhz
AD9364_Write_Reg(0x233,0xCB); // Write Rx Synth Fractional Freq Word[7:0]
AD9364_Write_Reg(0x234,0xCC); // Write Rx Synth Fractional Freq Word[15:8]
AD9364_Write_Reg(0x235,0x0C); // Write Rx Synth Fractional Freq Word[22:16]
AD9364_Write_Reg(0x232,0x00); // Write Rx Synth Integer Freq Word[10:8]
AD9364_Write_Reg(0x231,0x4B); // Write Rx Synth Integer Freq Word[7:0]
AD9364_Write_Reg(0x005,0x32); // Set LO divider setting
//tx_a 433mhz
AD9364_Write_Reg(0x273,0x11); // Write Tx Synth Fractional Freq Word[7:0]
AD9364_Write_Reg(0x274,0x5A); // Write Tx Synth Fractional Freq Word[15:8]
AD9364_Write_Reg(0x275,0x64); // Write Tx Synth Fractional Freq Word[22:16]
AD9364_Write_Reg(0x272,0x00); // Write Tx Synth Integer Freq Word[10:8]
AD9364_Write_Reg(0x271,0x56); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
AD9364_Write_Reg(0x005,0x32); // Set LO divider setting

 

//SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked)
//SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked)
for(count=0;count<1000;count++) // Check RX RF PLL lock status (0x247[1]==1 is locked)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x247);
if((temp_data&0x02)==0x02)
break;
}
if(count>=1000)
return 0;

for(count=0;count<1000;count++) // Check TX RF PLL lock status (0x287[1]==1 is locked)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x287);
if((temp_data&0x02)==0x02)
break;
}
if(count>=1000)
return 0;

//************************************************************
// Program Mixer GM Sub-table
//************************************************************
AD9364_Write_Reg(0x13F,0x02); // Start Clock
AD9364_Write_Reg(0x138,0x0F); // Addr Table Index
AD9364_Write_Reg(0x139,0x78); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x00); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x0E); // Addr Table Index
AD9364_Write_Reg(0x139,0x74); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x0D); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x0D); // Addr Table Index
AD9364_Write_Reg(0x139,0x70); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x15); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x0C); // Addr Table Index
AD9364_Write_Reg(0x139,0x6C); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x1B); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x0B); // Addr Table Index
AD9364_Write_Reg(0x139,0x68); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x21); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x0A); // Addr Table Index
AD9364_Write_Reg(0x139,0x64); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x25); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x09); // Addr Table Index
AD9364_Write_Reg(0x139,0x60); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x29); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x08); // Addr Table Index
AD9364_Write_Reg(0x139,0x5C); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x2C); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x07); // Addr Table Index
AD9364_Write_Reg(0x139,0x58); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x2F); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x06); // Addr Table Index
AD9364_Write_Reg(0x139,0x54); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x31); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x05); // Addr Table Index
AD9364_Write_Reg(0x139,0x50); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x33); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x04); // Addr Table Index
AD9364_Write_Reg(0x139,0x4C); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x34); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x03); // Addr Table Index
AD9364_Write_Reg(0x139,0x48); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x35); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x02); // Addr Table Index
AD9364_Write_Reg(0x139,0x30); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x3A); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x01); // Addr Table Index
AD9364_Write_Reg(0x139,0x18); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x3D); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x138,0x00); // Addr Table Index
AD9364_Write_Reg(0x139,0x00); // Gain
AD9364_Write_Reg(0x13A,0x00); // Bias
AD9364_Write_Reg(0x13B,0x3E); // GM
AD9364_Write_Reg(0x13F,0x06); // Write Words
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x13F,0x02); // Clear Write Bit
AD9364_Write_Reg(0x13C,0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
AD9364_Write_Reg(0x13C,0x00); // Delay ~1us (Dummy Write)
AD9364_Write_Reg(0x13F,0x00); // Stop Clock

//************************************************************
// Program Rx Gain Tables with SplitGainTable800MHz.csv
//************************************************************
AD9364_Write_Reg(0x137,0x1A); // Start Gain Table Clock
AD9364_Write_Reg(0x130,0x00); // Gain Table Index
AD9364_Write_Reg(0x131,0x00); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x01); // Gain Table Index
AD9364_Write_Reg(0x131,0x01); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x02); // Gain Table Index
AD9364_Write_Reg(0x131,0x02); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x03); // Gain Table Index
AD9364_Write_Reg(0x131,0x03); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x04); // Gain Table Index
AD9364_Write_Reg(0x131,0x04); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x05); // Gain Table Index
AD9364_Write_Reg(0x131,0x05); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x06); // Gain Table Index
AD9364_Write_Reg(0x131,0x06); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x07); // Gain Table Index
AD9364_Write_Reg(0x131,0x07); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x08); // Gain Table Index
AD9364_Write_Reg(0x131,0x08); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x09); // Gain Table Index
AD9364_Write_Reg(0x131,0x09); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x0A); // Gain Table Index
AD9364_Write_Reg(0x131,0x0A); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x0B); // Gain Table Index
AD9364_Write_Reg(0x131,0x0B); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x0C); // Gain Table Index
AD9364_Write_Reg(0x131,0x0C); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x0D); // Gain Table Index
AD9364_Write_Reg(0x131,0x0D); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x0E); // Gain Table Index
AD9364_Write_Reg(0x131,0x23); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x0F); // Gain Table Index
AD9364_Write_Reg(0x131,0x24); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x10); // Gain Table Index
AD9364_Write_Reg(0x131,0x43); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x11); // Gain Table Index
AD9364_Write_Reg(0x131,0x44); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x12); // Gain Table Index
AD9364_Write_Reg(0x131,0x45); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x13); // Gain Table Index
AD9364_Write_Reg(0x131,0x46); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x14); // Gain Table Index
AD9364_Write_Reg(0x131,0x47); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x15); // Gain Table Index
AD9364_Write_Reg(0x131,0x48); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x18); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x16); // Gain Table Index
AD9364_Write_Reg(0x131,0x43); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x17); // Gain Table Index
AD9364_Write_Reg(0x131,0x44); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x18); // Gain Table Index
AD9364_Write_Reg(0x131,0x45); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x19); // Gain Table Index
AD9364_Write_Reg(0x131,0x46); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x1A); // Gain Table Index
AD9364_Write_Reg(0x131,0x47); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x1B); // Gain Table Index
AD9364_Write_Reg(0x131,0x48); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x1C); // Gain Table Index
AD9364_Write_Reg(0x131,0x63); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x1D); // Gain Table Index
AD9364_Write_Reg(0x131,0x64); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x1E); // Gain Table Index
AD9364_Write_Reg(0x131,0x65); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x1F); // Gain Table Index
AD9364_Write_Reg(0x131,0x66); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x20); // Gain Table Index
AD9364_Write_Reg(0x131,0x67); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x21); // Gain Table Index
AD9364_Write_Reg(0x131,0x68); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x22); // Gain Table Index
AD9364_Write_Reg(0x131,0x69); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x23); // Gain Table Index
AD9364_Write_Reg(0x131,0x6A); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x24); // Gain Table Index
AD9364_Write_Reg(0x131,0x6B); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x25); // Gain Table Index
AD9364_Write_Reg(0x131,0x6C); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x26); // Gain Table Index
AD9364_Write_Reg(0x131,0x6D); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x27); // Gain Table Index
AD9364_Write_Reg(0x131,0x6E); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x130,0x28); // Gain Table Index
AD9364_Write_Reg(0x131,0x6F); // Ext LNA,0x Int LNA,0x & Mixer Gain Word
AD9364_Write_Reg(0x132,0x38); // TIA & LPF Word
AD9364_Write_Reg(0x133,0x20); // DC Cal bit & Dig Gain Word
AD9364_Write_Reg(0x137,0x1E); // Write Words
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay 3 ADCCLK/16 cycles
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x137,0x1A); // Clear Write Bit
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x134,0x00); // Dummy Write to delay ~1us
AD9364_Write_Reg(0x137,0x00); // Stop Gain Table Clock
//************************************************************
// Setup Rx AGC Slow Attack/Hybrid Registers
//************************************************************
AD9364_Write_Reg(0x0FA,0xEA); // Gain Control Mode Select
AD9364_Write_Reg(0x0FB,0x00); // Full Table/Digital Gain Select
AD9364_Write_Reg(0x0FC,0x03); // ADC Overrange Sample Size
AD9364_Write_Reg(0x0FD,0x28); // Max Full/LMT Gain Table Index
AD9364_Write_Reg(0x0FE,0x48); // Peak Overload Wait Time
AD9364_Write_Reg(0x100,0xAF); // Max Digital Gain
AD9364_Write_Reg(0x101,0x0A); // AGC Inner High Threshold
AD9364_Write_Reg(0x103,0x08); // Large LMT Step Size
AD9364_Write_Reg(0x104,0x2F); // ADC Small Overload Threshold
AD9364_Write_Reg(0x105,0x3A); // ADC Large Overload Threshold
AD9364_Write_Reg(0x106,0x22); // ADC Overload Step Sizes
AD9364_Write_Reg(0x107,0x31); // Large LMT Overload Threshold
AD9364_Write_Reg(0x108,0x39); // Small LMT Overload Threshold
AD9364_Write_Reg(0x111,0x0A); // Settling Delay
AD9364_Write_Reg(0x11A,0x27); // Initial LMT Gain Limit
AD9364_Write_Reg(0x120,0x0C); // Prevent Inc & AGC Inner Low Thresh
AD9364_Write_Reg(0x121,0xAA); // LMT Overload Exceeded Counters
AD9364_Write_Reg(0x122,0xAA); // ADC Overload Exceeded Counters
AD9364_Write_Reg(0x123,0x11); // AGC Inner High & Low Step Sizes
AD9364_Write_Reg(0x124,0xF5); // Gain Update Counter<7:0>
AD9364_Write_Reg(0x125,0x3B); // Gain Update Counter<15:8>
AD9364_Write_Reg(0x128,0x03); // Digital Sat Exceeded Counter
AD9364_Write_Reg(0x129,0x56); // AGC Outer High & Low Thresholds
AD9364_Write_Reg(0x12A,0x22); // AGC Outer High & Low Step Sizes
//************************************************************
// RX Baseband Filter Tuning (Real BW: 1.350000 MHz) 3dB Filter
// Corner @ 1.890000 MHz)
//************************************************************
AD9364_Write_Reg(0x1FB,0x01); // RX Freq Corner (MHz)
AD9364_Write_Reg(0x1FC,0x2D); // RX Freq Corner (Khz)
AD9364_Write_Reg(0x1F8,0x3A); // Rx BBF Tune Divider[7:0]
AD9364_Write_Reg(0x1F9,0x1E); // RX BBF Tune Divider[8]

AD9364_Write_Reg(0x1D5,0x3F); // Set Rx Mix LO CM
AD9364_Write_Reg(0x1C0,0x03); // Set GM common mode
AD9364_Write_Reg(0x1E2,0x02); // Enable Rx1 Filter Tuner
AD9364_Write_Reg(0x1E3,0x02); // Enable Rx2 Filter Tuner
AD9364_Write_Reg(0x016,0x80); // Start RX Filter Tune
//WAIT_CALDONE RXFILTER,0x2000 // Wait for RX filter to tune,0x Max Cal Time: 35.990 us (Done when 0x016[7]==0)
for(count=0;count<2000;count++)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x016);
if((temp_data&0x80)==0x00)
break;
}
if(count>=2000)
return 0;


AD9364_Write_Reg(0x1E2,0x03); // Disable Rx Filter Tuner (Rx1)
AD9364_Write_Reg(0x1E3,0x03); // Disable Rx Filter Tuner (Rx2)
//************************************************************
// TX Baseband Filter Tuning (Real BW: 1.350000 MHz) 3dB Filter
// Corner @ 2.160000 MHz)
//************************************************************
AD9364_Write_Reg(0x0D6,0x33); // TX BBF Tune Divier[7:0]
AD9364_Write_Reg(0x0D7,0x1E); // TX BBF Tune Divider[8]

AD9364_Write_Reg(0x0CA,0x22); // Enable Tx Filter Tuner
AD9364_Write_Reg(0x016,0x40); // Start Tx Filter Tune
//WAIT_CALDONE TXFILTER,0x2000 // Wait for TX filter to tune,0x Max Cal Time: 18.417 us (Done when 0x016[6]==0)
for(count=0;count<2000;count++)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x016);
if((temp_data&0x40)==0x00)
break;
}
if(count>=2000)
return 0;


AD9364_Write_Reg(0x0CA,0x26); // Disable Tx Filter Tuner (Both Channels)
//************************************************************
// RX TIA Setup: Setup values scale based on RxBBF calibration
// results. See information in Calibration Guide.
//************************************************************
//SPIRead 1EB // Read RXBBF C3(MSB)
//SPIRead 1EC // Read RXBBF C3(LSB)
//SPIRead 1E6 // Read RXBBF R2346
AD9364_Write_Reg(0x1DB,0xE0); // Set TIA selcc[2:0]
AD9364_Write_Reg(0x1DD,0x1A); // Set RX TIA1 C MSB[6:0]
AD9364_Write_Reg(0x1DF,0x1A); // Set RX TIA2 C MSB[6:0]
AD9364_Write_Reg(0x1DC,0x40); // Set RX TIA1 C LSB[5:0]
AD9364_Write_Reg(0x1DE,0x40); // Set RX TIA2 C LSB[5:0]

//************************************************************
// TX Secondary Filter Calibration Setup: Real Bandwidth
// 1.350000MHz,0x 3dB Corner @ 6.750000MHz
//************************************************************
AD9364_Write_Reg(0x0D2,0x2F); // TX Secondary Filter PDF Cap cal[5:0]
AD9364_Write_Reg(0x0D1,0x03); // TX Secondary Filter PDF Res cal[3:0]
AD9364_Write_Reg(0x0D0,0x59); // Pdampbias

//************************************************************
// ADC Setup: Tune ADC Performance based on RX analog filter tune
// corner. Real Bandwidth: 1.335552 MHz,0x ADC Clock Frequency:
// 61.440000 MHz. The values in registers 0x200 - 0x227 need to be
// calculated using the equations in the Calibration Guide.
//************************************************************
//SPIRead 1EB // Read RxBBF C3 MSB after calibration
//SPIRead 1EC // Read RxBBF C3 LSB after calibration
//SPIRead 1E6 // Read RxBBF R3 after calibration

AD9364_Write_Reg(0x200,0x00);
AD9364_Write_Reg(0x201,0x00);
AD9364_Write_Reg(0x202,0x00);
AD9364_Write_Reg(0x203,0x24);
AD9364_Write_Reg(0x204,0x24);
AD9364_Write_Reg(0x205,0x00);
AD9364_Write_Reg(0x206,0x00);
AD9364_Write_Reg(0x207,0x27);
AD9364_Write_Reg(0x208,0x9D);
AD9364_Write_Reg(0x209,0x1D);
AD9364_Write_Reg(0x20A,0x25);
AD9364_Write_Reg(0x20B,0x9B);
AD9364_Write_Reg(0x20C,0x27);
AD9364_Write_Reg(0x20D,0x9B);
AD9364_Write_Reg(0x20E,0x15);
AD9364_Write_Reg(0x20F,0x28);
AD9364_Write_Reg(0x210,0x29);
AD9364_Write_Reg(0x211,0x28);
AD9364_Write_Reg(0x212,0x24);
AD9364_Write_Reg(0x213,0x25);
AD9364_Write_Reg(0x214,0x24);
AD9364_Write_Reg(0x215,0x26);
AD9364_Write_Reg(0x216,0x27);
AD9364_Write_Reg(0x217,0x26);
AD9364_Write_Reg(0x218,0x2E);
AD9364_Write_Reg(0x219,0x86);
AD9364_Write_Reg(0x21A,0x0A);
AD9364_Write_Reg(0x21B,0x09);
AD9364_Write_Reg(0x21C,0x86);
AD9364_Write_Reg(0x21D,0x0A);
AD9364_Write_Reg(0x21E,0x09);
AD9364_Write_Reg(0x21F,0x86);
AD9364_Write_Reg(0x220,0x0A);
AD9364_Write_Reg(0x221,0x13);
AD9364_Write_Reg(0x222,0x13);
AD9364_Write_Reg(0x223,0x40);
AD9364_Write_Reg(0x224,0x40);
AD9364_Write_Reg(0x225,0x2C);
AD9364_Write_Reg(0x226,0x00);
AD9364_Write_Reg(0x227,0x00);

//************************************************************
// Tx Quadrature Calibration Settings
//************************************************************
//SPIRead 0A3 // Masked Read: Read lower 6 bits,0x overwrite [7:6] below
AD9364_Write_Reg(0x0A0,0x15); // Set TxQuadcal NCO frequency
AD9364_Write_Reg(0x0A3,0x00); // Set TxQuadcal NCO frequency (Only update bits [7:6])
AD9364_Write_Reg(0x0A1,0x7B); // Set TxQuadcal M[1:0]
AD9364_Write_Reg(0x0A9,0xFF); // Set Tx Quad Cal Count
AD9364_Write_Reg(0x0A2,0x7F); // Set Tx Quad Cal Kexp
AD9364_Write_Reg(0x0A5,0x01); // Set Tx Quad Cal Magnitude Threshhold
AD9364_Write_Reg(0x0A6,0x01); // Set Tx Quad Cal Magnitude Threshhold
AD9364_Write_Reg(0x0AA,0x16); // Set Tx Quad Cal Gain Table index
AD9364_Write_Reg(0x0A4,0xF0); // Set Tx Quad Cal Setting Count
AD9364_Write_Reg(0x0AE,0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used

AD9364_Write_Reg(0x193,0x3F); // BBDC Cal setting
AD9364_Write_Reg(0x190,0x0F); // Set BBDC tracking shift M value,0x only applies when BB DC tracking enabled
AD9364_Write_Reg(0x194,0x01); // BBDC Cal setting
AD9364_Write_Reg(0x016,0x01); // Start BBDC offset cal
//WAIT_CALDONE BBDC,0x2000 // BBDC Max Cal Time: 40400.000 us. Cal done when 0x016[0]==0
for(count=0;count<2000;count++)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x016);
if((temp_data&0x01)==0x00)
break;
}
if(count>=2000)
return 0;

#if 1
//while(1);
AD9364_Write_Reg(0x185,0x20); // Set RF DC offset Wait Count
AD9364_Write_Reg(0x186,0x32); // Set RF DC Offset Count[7:0]
AD9364_Write_Reg(0x187,0x24); // Settings for RF DC cal
AD9364_Write_Reg(0x18B,0x83); // Settings for RF DC cal
AD9364_Write_Reg(0x188,0x05); // Settings for RF DC cal
AD9364_Write_Reg(0x189,0x30); // Settings for RF DC cal
AD9364_Write_Reg(0x016,0x02); // RFDC Max Cal Time: 184086.000 us
//WAIT_CALDONE RFDC,0x2000 // Wait for cal to complete (Done when 0x016[1]==0)
for(count=0;count<2000;count++)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x016);
if((temp_data&0x02)==0x00)
break;
}
if(count>=2000)
return 0;

 

AD9364_Write_Reg(0x016,0x10); // TXQuad Max Cal Time: 9446.400 us
//WAIT_CALDONE TXQUAD,0x2000 // Wait for cal to complete (Done when 0x016[4]==0)
for(count=0;count<2000;count++)
{
delay_ms(1);
temp_data=AD9364_Read_Reg(0x016);
if((temp_data&0x10)==0x00)
break;
}
if(count>=2000)
return 0;
#endif

AD9364_Write_Reg(0x168,0x03); // Set RX Quadcal Tone Level
AD9364_Write_Reg(0x16E,0x25); // Set Rx Gain index to use during RX Quadcal
AD9364_Write_Reg(0x16A,0x75); // Set Kexp Phase
AD9364_Write_Reg(0x16B,0x15); // Set Kexp Amplitude
AD9364_Write_Reg(0x169,0xCF);
AD9364_Write_Reg(0x18B,0xAD);
AD9364_Write_Reg(0x012,0x02); // Cals done,0x Set PPORT Config
AD9364_Write_Reg(0x013,0x01); // Set ENSM FDD/TDD bit
AD9364_Write_Reg(0x015,0x04); // Set Dual Synth Mode,0x FDD External Control bits properly


//************************************************************
// Set Tx Attenuation: Tx1: 10.00 dB,0x Tx2: 10.00 dB
//************************************************************
//AD9364_Write_Reg(0x073,0x28);
//AD9364_Write_Reg(0x074,0x00);
//AD9364_Write_Reg(0x075,0x28);
//AD9364_Write_Reg(0x076,0x00);

//************************************************************
// Setup RSSI and Power Measurement Duration Registers
//************************************************************
/*
AD9364_Write_Reg(0x150,0x0B); // RSSI Measurement Duration 0,0x 1
AD9364_Write_Reg(0x151,0x00); // RSSI Measurement Duration 2,0x 3
AD9364_Write_Reg(0x152,0xFF); // RSSI Weighted Multiplier 0
AD9364_Write_Reg(0x153,0x00); // RSSI Weighted Multiplier 1
AD9364_Write_Reg(0x154,0x00); // RSSI Weighted Multiplier 2
AD9364_Write_Reg(0x155,0x00); // RSSI Weighted Multiplier 3
AD9364_Write_Reg(0x156,0x00); // RSSI Delay
AD9364_Write_Reg(0x157,0x00); // RSSI Wait
AD9364_Write_Reg(0x158,0x0D); // RSSI Mode Select
AD9364_Write_Reg(0x15C,0x69); // Power Measurement Duration
*/
//20180302 test
AD9364_Write_Reg(0x150,0x09); // RSSI Measurement Duration 0,0x 1
AD9364_Write_Reg(0x151,0x00); // RSSI Measurement Duration 2,0x 3
AD9364_Write_Reg(0x152,0xFF); // RSSI Weighted Multiplier 0
AD9364_Write_Reg(0x153,0x00); // RSSI Weighted Multiplier 1
AD9364_Write_Reg(0x154,0x00); // RSSI Weighted Multiplier 2
AD9364_Write_Reg(0x155,0x00); // RSSI Weighted Multiplier 3
AD9364_Write_Reg(0x156,0x00); // RSSI Delay
AD9364_Write_Reg(0x157,0x00); // RSSI Wait
AD9364_Write_Reg(0x158,0x11); // RSSI Mode Select
AD9364_Write_Reg(0x15C,0x69); // Power Measurement Duration

 

AD9364_Write_Reg(0x002,0x5E); // Set # transmitters enabled
AD9364_Write_Reg(0x003,0x5E); // Set # receivers enabled

AD9364_Write_Reg(0x014,0x63);
//AD9364_Write_Reg(0x014,0x23);

//while(1);
return 1;
}

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↧

Re: Manually generate sequence file

April 11, 2018, 12:39 am
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About 1a):

For those who are interessted: I checked the access with an oscilloscope. The five lines are performed as a single safeload write:

This is also true when written as a sequence. Therefore the display in Sigma Studio is just misleading, but seems to work.

↧

Re: AD7761 Synchronization

April 11, 2018, 12:39 am
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Hi,

 

Usually they should have common RESET, SYNC, MCLK and VREF inputs. So if you could make also the reference input in star point it would be better.

 

Thanks,

Jellenie

↧

Re: How to use AD7124 to measure Load cell having 2mv/V and excitation voltage of 5-12V

April 11, 2018, 12:42 am
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Hi JellenieR,

Ok understood. But I am looking for Ratiometric meaurement which is possible only if both ADC and Loadcell shared same voltage source to cancel out Reference voltage variation. But, by using 5V for Loadcell and 3.3V for ADC reference , we can't think of Ratio metric measurement.

 

By the way, should we go to ADC which support ADC reference of up to 5V to get better accuracy?.

 

Have you worked on any load cell?,Coz, I am looking  for Loadcell which will have minimum of 3V excitation.If you aware of load cell have the above, please let me know.

 

 

Thanks,

Muthu 

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Search

Re: How to use AD7124 to measure Load cell having 2mv/V and excitation voltage of 5-12V

April 11, 2018, 12:51 am
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Hi,

 

I have worked and tried using the AD719x for load cell application and AD7124 for temperature measurements. Both can operate in this type of application with optimum performance. But your target specification will define whether the part will suite your application. So I think you can either change your load cell with 3.3V excitation voltage or consider using AD719x for 5V operation. Just define first your target resolution or performance so you can decide well.

 

Thanks,

Jellenie

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↧

Re: Where can I find the instruction of the reference design?

April 11, 2018, 12:57 am
↧

Re: Problem with AD8336 model in LTspice

April 10, 2018, 7:39 pm
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Hi,

 

1. In Fig. 4.5 of the reference pdf file you attached, there are resistors R7 and R8 in the output but in your schematic output is floating. Try adding these resistors in the output. Also, voltage at VGPOS = -1.0 instead of 0.5V in your schematic.

2. Your input might be too fast and high. Change it to ex. 500mV amplitude and frequency of 100k then increase also simulation time to around 20us.

3. Finally, for now please add this statement in your LTspice test schematic ".options cshunt=1e-15".

 

Please check the attached file for your reference.

Hope this helps.

↧

Re: How to acquire data from AD9689 with Matlab ?

April 11, 2018, 1:03 am
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Hi Michael,

 

Thank you very much for your answer. I well understood that I don't need to use the VISA commands.

So, I directly start accessing ACE as follow :

 

"% Access ACE

NET.addAssembly('D:\APP\ACE\Client\AnalogDevices.Csa.Remoting.Clients.dll');

import AnalogDevices.Csa.Remoting.Clients.*;

clientManager = ClientManager.Create();

client = clientManager.CreateRequestClient(2357);

client.ContextPath = '\System\Subsystem_1\AD9689-2600EBZ\AD9689';"

 

Now, if I well understood what you told me, I am able to send register read / right and data capture commands.

Could you give me some exemple command for this please.

I would like the command for these pseudo codes :

client.dataCapture('65536 samples');

client.registerWrite('address','value');

client.registerRead('address');

 

I'm not sure to understand what you mean here : "If you want to select the attached hardware in the script as opposed to doing that in ACE", could you explain more please.

 

Thanks a lot for your help !!

 

Regards,

Logan

↧

Re: LTC3114 instability when Iout > 150 mA

April 11, 2018, 12:23 am
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Thanks for your reply!

 

1. I've decreased the value as you suggested, unfortunately it does not make a difference. However I agree that if it is on the limit we should decrease the value.

2. Sorry that was an error in my screenshot, the 100 uF capacitor is indeed installed. I've also measured the output capacitance to be 120 uF in total. I have calculated the compensation with LTpowerCAD over operating range and it should be stable with my values. If I decrease Rz to 39k instability still occurs, however now at 400 mA output current so we can assume there is something wrong with the compensation. I am a bit at a loss because LTpowerCAT gives me good phase margin at my operating parameters yet it still becomes unstable.

3. I know, I have taken care to keep a solid ground plane, keep decoupling and output capacitances close to the LT3114, have solid GND via stitching etc. You can see my layout in the picture below:

 

LTC3114 2-layer layout

 

I have also noticed that the duty cycle changes with output current, however shouldn't this stay the same as the input and output voltaged don't change?

↧
↧

ADV7611/7612 Map address setting

April 11, 2018, 1:06 am
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Hi

We used to use following setting at the biginning of a HDMI EVB script,

and I undersnatnd these Map are programable.

 

98 F4 80 ; CEC                 10000000   
98 F5 7C ; INFOFRAME   01111100
98 F8 4C ; DPLL               01001100      
98 F9 64 ; KSV                  01100100
98 FA 6C ; EDID               01101100
98 FB 68 ; HDMI               01101000
98 FD 44 ; CP                   01000100

 

Are there any limitation/restriction to set Map address on HDMI Rx products?

From above script example, it looks MSB is all set to 0 except CEC, and LSB is all set to 0.

Since LSB of the first address is used for read(0)/write(1), LSB of the Map address setting doesn't take any effect? 

 

A customer is considering to change CP Map address from 0x44 to something else due device address conflict on same I2C line like

98 FD 45 ; CP   not good? same meaning as 0x44

98 FD 46 ; CP   good? 

 

Regards,

Tomoto

↧

Re: OSC connection timeout on fmcomms5 + zcu102

April 11, 2018, 1:19 am
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Hi,

 

I find a solution for this DMA problem. I remove "pl_clk2" clock output pin on MPSoC IP core. Then reconnect both DMA master AXI aclk pin to "pl_clk0" and also change both DMA AXI bus width from 64 to 128. I also change devicetree where I change both DMA bus width from 64 to 128. Basically, I just replicate the similar configuration of FMCOMMS2 ZCU102 HDL project onto my FMCOMMS5 project. Finally, it works. OSC realtime plotting waveform is normal and "cat /proc/interrupt" observe adc_dma properly working. I guess "pl_clk2" is not properly working or only working under certain PLL setting since zyqnmp mpsoc is upgraded a lot comparing to the zynq 7. 

  Furthermore, I also want to enable ADF5355 on FMCOMMS5. So I copy the old devicetree from "zynq-zc706-adv7511-ad9361-fmcomms5-ext-lo-adf5355.dts" . Change "gpios" to "gpios = <&gpio 142 0>;" and including my modified devicetree "zynqmp-zcu102-rev10-ad9361-fmcomms5_mod.dts". Then compile it and upload to SD card. I can find an extra adf5355 device is added onto Linux kernel. OSC still run as normal and read properties of adf5355. However, adf5355 does not properly works. It won't synthesis any carrier frequency. I can observe nothing on frequency spectrum when I use OSC to send out preload waveform through DAC buffer feature. Then spectrum becomes normal if switch back to ad9361 internal synthesizer. On this devicetree "<&gpio 142 0>" is the only thing I changed. Is there anything I miss? Thank you for the help.

 

Regards

↧
Search

ADRF6720 VPTAT output characteristics ?

April 11, 2018, 1:30 am
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ADRV9371 HDL manual setup on ZC706

April 11, 2018, 1:32 am
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Hi,

 

I am having issues with the ADRV9371 HDL manual setup on ZC706: Setting up the 9361 using Vivado 2016.2 worked fine and documentation was excellent. 

 

Can you point me to the latest relevant repository to download the reference design (project & library) ? The pointer ADRV9371 HDL Reference Design [Analog Devices Wiki]  seems to be outdated and pointing to code that is supported only by an older vivado version (2015.4).

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↧

Re: sample rate detection

April 11, 2018, 1:33 am
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hello Mr. Dave

 

Actually, i use  sigmadsp EVAL-ADAU1452 and i juste want to know if y-a-t-il possibilité de detecter la frequence du signal d'entrée sur ce dsp?
si oui, peut on utiliser ce detecteur pour commuter differents signaux?

 

Best regards

 

imad

↧

Re: LTspice, Capacitor "Series Inductance" and HF Spikes

April 11, 2018, 12:08 am
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dulcevida, I sincerely appreciate your kind assistance in bringing this to the attention of Analog's LTspice expert.  I look forward to hearing more.  In the meantime, perhaps I could ask you another, related question...

 

BACKGROUND INFO

My application is a switch-mode power supply for 12V automotive use, supplying 5V @200mA (peak) to an MCU and CAN Transciever circuitry.  Sustain current draw by my circuit when the vehicle's CAN is awake will be around 80mA.  (I know this because I have an existing product on the market with linear power supply which I used in my testing of current draw.  We are redesigning the power supply to ensure operation during cold start, using the LT8362.) When the vehicle's CAN is sleeping, the total device current (including PSU) draw will drop to less than 4mA.  Vcc-min for the CAN transceiver and MCU is 4.50V.  The aim is to maintain a steady 4.7V-5V to the circuit even during cold-cranking (where the vehicle's battery voltage could drop to as low as 2.8V).  So long as I don't add Series Inductance in my capacitors in LTspice, the LT8362 circuit simulates as expected.  A reverse polarity protection diode (DFLS260) at the input will cause a further voltage drop to as low as 2.44V, which is the lowest the LT8362 will see at Vin.  (DFLS60 is 60Vmax but is protected by a TPSMC36CA TVS diode with Vc=49.9V, which is placed before the Schottky in the circuit.)

 

In my LTspice (version IV for MacOS X) simulations (which does not consider the PCM layout, I know), I am finding the Peak-to-Peak noise (ripple and HF spikes) is 7.6mV when in BUCK mode (>6V at Vin), and 28mVp-p while in BOOST mode (when the car battery voltage drops to 2.8V).  I honestly do not know what the acceptable level of noise is for a CAN transceiver's Vcc, but even 28mVp-p is only 0.6% of 5.0V, which I guess can be considered "low."  I did simulate other variants of my circuit using a BL02RN1-R62 Ferrite BEAD and 47uF EEU-FR1H470 capacitor, which yields 880uVp-p in BUCK mode and 3.2mVp-p in BOOST.  Another circuit variant I tried uses a 0.33-ohm resistor (actually, three 1-ohm resistors in parallel, which would be cheaper than a single 0.33-ohm resistor) on the output, followed by the same 47uF electrolytic lowESR capacitor, yielding 517uVp-p noise in BUCK mode and 2.4mVp-p in BOOST. Output Voltage never dropped below 4.996V in any of the simulations regardless of input voltage dropping to 2.8V and with up to 200mA load current.  But again, these simulation results were performed without any Series Inductance on my capacitors, so actual peak-to-peak noise will likely be higher than this.

 

So why did I choose the LT8362 for my SEPIC application?  Because Vin-max = 60V.  That is important because my TVS choice is Vc=50V.  Any switcher chips with Vin lower than 50V are not acceptable.  And when considering jump starts and Load Dumps, the TPSMC36CA with its Vc=50V is really the best choice for circuit protection in a 12V vehicle application.

 

I am still new to switching power supply design, and I've been running a number of simulations in LTspice to determine the best component picks to make for the purpose of building a test circuit.  I am well aware that the PCB layout plays a major role in peak-to-peak output noise and the overall performance of the circuit.  But for now, I am pondering 5V output noise in LTspice in conjunction with my coupled inductor choice.

 

Even though I don't expect more than 200mA peak current draw, I am adding a safety margin and designing this power supply for a maximum current output of 5V@300mA, which again would be very short-term peak current draw.  Sustained draw will not exceed 80-90mA (while the Ignition is ON and while CAN is awake).  Doing the LT8362 datasheet SEPIC calculations for a 0.3A 5V output, I get the following:

 

  • Dmax = 0.667 (based on Vin-min = 2.8V and my Schottky diode choice of DFLS260-7)
  • Rt = 20k-ohm (2MHz operation), Bias pin tied to GND
  • Isw-max-avg = 900mA
  • Isw-peak = 1.2A
  • Isw = x * Isw-max-avg = 0.6A ("x" should be between 0.5 and 0.8, so I chose 0.65)
  • Delta-IL1 = Delta-IL2 = 0.5 x Isw = 0.3A
  • IL1peak = IL1max + 0.5 * Delta-IL1 = 750mA
  • IL2peak = IL2max + 0.5 * Delta-IL2 = 450mA

 

Based on the above calculations, the minimum inductance for a coupled inductor is low enough to qualify use of either 2.2uH or 4.7uH (per inductor).  (The LT8362 datasheet's 5V example circuit uses 2.2uH.)  After running LTspice simulations and viewing peak-to-peak noise on the 5V output, I decided on a 4.7uH inductor.  The Wurth inductor shown in the 5V-output datasheet example is physically too large for my application at 12.5 x 12.5mm, and no surprise since that example circuit is designed for a 1A output.  So in my test circuit in LTspice, I am now using a Wurth 744877004 coupled inductor (4.8uH, Irms=2.55A, DCR=64m-ohm), which is 7.3x7.3mm in size. (The Wurth 74489440047 is Irms=1.85A, which should be adequate for my 0.3A application, but there is no LTspice model for that inductor.)

 

MY QUESTION

When comparing inductor brands, I am finding a somewhat large pricing disparity.  Wurth seems to be the Mercedes Benz of inductors, as shown in this coupled inductor comparison (all roughly 7.5x7.5mm in size and all SHIELDED):

 

  • WURTH 744877004, 4.7uH, Irms=2.55A, DCR=64m-ohm, Price=US$1.53EA per 1000pcs
  • EATON DRQ74-4R7-R, 4.7uH, Irms=1.67A, DCR=51m-ohm, Price=US$0.84EA per 1000pcs
  • COILCRAFT MSD7342-472ML, 4.7uH, Irms=1.74A, DCR=51m-ohm, Price=US$0.80EA per 1000pcs
  • BOURNS SRF0703-2R2M, 4.7uH, Irms=2.00A, DCR=66m-ohm, Price=US$0.36EA per 1000pcs

 

Do you know why the BOURNS is so much cheaper than the WURTH? They all are coupled inductors.  

 

One thing I greatly appreciate about the WURTH coupled inductors is the fact I can conveniently simulate them in LTspice, but price really does matter in my application.  I am inclined to go with the BOURNS based on price, but I want to know why the other coupled inductors are so much more expensive at the same quantity. Any guidance you can offer on coupled inductor selection for my application would be greatly appreciated.

 

Thank you.

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Re: Interrupt Latency on 215xx

April 11, 2018, 1:41 am
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Hi Jon,

 

I have tested with the attached code and I do not see any variation that you reported. Can you please check this code and and let me know if I have overlooked something in order to replicate your issue.

 

Thanks,

Jithul

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