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Re: Signal latancy in the ADV7181C and ADV7392.

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1) As long as the digital interfaces match, both physical and logical then you should be able to interface ADI devices to the Intersil devices.  I am not familiar with those specific two parts.

 

2) What you have selected should be good, I have no better solution

 

3) I don't know how the Intersil parts work, however I would assume that what goes into the transmitter comes out the receiver, this includes the pixel clock which must be the same on both ends of the fiber.  If the pixel clocks don't match then you will have over/under flow issues.

 

4)  for NTSC LLC = 13.5MHz, assumes you are running YCbCr 444 or 422, over 24 or 16 bit bus.  If you have 8 bit bus then it will be 422 at 27MHz

 

5) The device works with single ended inputs only.  You will need to buffer the differential signals and make sure they're the right amplitude.  Page 266, Figure 82 of the ADV7181C manual_revC shows you how to connect the RGB signals to the device.  Note that the inputs are AC coupled so the signal may not need to be ground referenced but can be bias another level.

 

6) Follow Figure 82.  Also look at the last row of Table 4 to see how to wire in two sets of RGB

 

7) Digital output levels are defined in Table 1,  basically they are LVCMOS levels.

 

8) Digital inputs are defined in Table 1, basically that are LVCOMS levels.

 

9) Yes all timing delays are based on the pixel clock rate.


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